[AArch64][x86] add tests for add/sub signbits fold; NFC

As discussed/shown in D57401, we are missing a fold for
subtract of 0/1 --> add 0/-1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352678 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/AArch64/bool-ext-inc.ll b/test/CodeGen/AArch64/bool-ext-inc.ll
index 7fc451e4d75d2ca1533dc6b7e3f418a0ee85257f..2b702f9644a86b9c15c7a9a95eb21c05918fd4d0 100644 (file)
--- a/test/CodeGen/AArch64/bool-ext-inc.ll
+++ b/test/CodeGen/AArch64/bool-ext-inc.ll
@@ -27,3 +27,34 @@ define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x
   ret <4 x i32> %s
 }
 
+define i32 @assertsext_sub_1(i1 signext %cond, i32 %y) {
+; CHECK-LABEL: assertsext_sub_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x1
+; CHECK-NEXT:    sub w0, w1, w8
+; CHECK-NEXT:    ret
+  %e = zext i1 %cond to i32
+  %r = sub i32 %y, %e
+  ret i32 %r
+}
+
+define i32 @assertsext_add_1(i1 signext %cond, i32 %y) {
+; CHECK-LABEL: assertsext_add_1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub w0, w1, w0
+; CHECK-NEXT:    ret
+  %e = zext i1 %cond to i32
+  %r = add i32 %e, %y
+  ret i32 %r
+}
+
+define i32 @assertsext_add_1_commute(i1 signext %cond, i32 %y) {
+; CHECK-LABEL: assertsext_add_1_commute:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub w0, w1, w0
+; CHECK-NEXT:    ret
+  %e = zext i1 %cond to i32
+  %r = add i32 %y, %e
+  ret i32 %r
+}
+

diff --git a/test/CodeGen/X86/bool-ext-inc.ll b/test/CodeGen/X86/bool-ext-inc.ll
index 4c81d05ee1f4e8b69c778fbbcb15506343f90a6c..cfd6dc8c62c7f2f751f9bcf645f52b5ea844dc55 100644 (file)
--- a/test/CodeGen/X86/bool-ext-inc.ll
+++ b/test/CodeGen/X86/bool-ext-inc.ll
@@ -127,3 +127,37 @@ define <4 x i32> @zextbool_sub_vector(<4 x i32> %cmp1, <4 x i32> %cmp2, <4 x i32
   ret <4 x i32> %s
 }
 
+define i32 @assertsext_sub_1(i1 signext %cond, i32 %y) {
+; CHECK-LABEL: assertsext_sub_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    andl $1, %edi
+; CHECK-NEXT:    subl %edi, %eax
+; CHECK-NEXT:    retq
+  %e = zext i1 %cond to i32
+  %r = sub i32 %y, %e
+  ret i32 %r
+}
+
+define i32 @assertsext_add_1(i1 signext %cond, i32 %y) {
+; CHECK-LABEL: assertsext_add_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    subl %edi, %eax
+; CHECK-NEXT:    retq
+  %e = zext i1 %cond to i32
+  %r = add i32 %e, %y
+  ret i32 %r
+}
+
+define i32 @assertsext_add_1_commute(i1 signext %cond, i32 %y) {
+; CHECK-LABEL: assertsext_add_1_commute:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    subl %edi, %eax
+; CHECK-NEXT:    retq
+  %e = zext i1 %cond to i32
+  %r = add i32 %y, %e
+  ret i32 %r
+}
+