This is a trivial point fix. Terminator instructions aren't scheduled, so
we shouldn't expect to be able to remap them.
This doesn't affect Hexagon and PPC because their terminators are always
hardware loop backbranches that have no register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373762
91177308-0d34-0410-b5e6-
96231b3b80d8
// Now remap every instruction in the loop.
for (MachineInstr &MI : *BB) {
- if (MI.isPHI())
+ if (MI.isPHI() || MI.isTerminator())
continue;
for (MachineOperand &MO : MI.uses()) {
if (!MO.isReg() || MO.getReg().isPhysical() || MO.isImplicit())