Revert "GlobalISel: Handle llvm.read_register"

This reverts commit r373294. It broke Clang's
CodeGen/arm64-microsoft-status-reg.cpp:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/18483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373310 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/GlobalISel/IRTranslator.cpp b/lib/CodeGen/GlobalISel/IRTranslator.cpp
index e1cfb96e13c2d4be2010bb23d2981cf94c03175a..37ac96e52905eb7745887c06b5266f1d0d84f7fb 100644 (file)
--- a/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1523,21 +1523,6 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
   case Intrinsic::sideeffect:
     // Discard annotate attributes, assumptions, and artificial side-effects.
     return true;
-  case Intrinsic::read_register: {
-    Value *Arg = CI.getArgOperand(0);
-    const Metadata *MD = cast<MetadataAsValue>(Arg)->getMetadata();
-    const MDString *RegStr = cast<MDString>(cast<MDNode>(MD)->getOperand(0));
-
-    auto *TLI = MF->getSubtarget().getTargetLowering();
-    Register Dst = getOrCreateVReg(CI);
-    EVT VT = TLI->getValueType(*DL, CI.getType());
-    Register Reg = TLI->getRegisterByName(RegStr->getString().data(), VT, *MF);
-    if (!Reg.isValid())
-      return false;
-
-    MIRBuilder.buildCopy(Dst, Reg);
-    return true;
-  }
   }
   return false;
 }

diff --git a/test/CodeGen/AMDGPU/GlobalISel/read_register.ll b/test/CodeGen/AMDGPU/GlobalISel/read_register.ll
deleted file mode 100644 (file)
index 3bd1699..0000000
--- a/test/CodeGen/AMDGPU/GlobalISel/read_register.ll
+++ /dev/null
@@ -1,2 +0,0 @@
-; Runs original SDAG test with -global-isel
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -verify-machineinstrs < %S/../read_register.ll | FileCheck -enable-var-scope %S/../read_register.ll

diff --git a/test/CodeGen/AMDGPU/read_register.ll b/test/CodeGen/AMDGPU/read_register.ll
index 2d38528d058a96d35ad5358c781f111e81d98b7a..8fe9e7f3f111d18edae9c0e527847efdcb492eee 100644 (file)
--- a/test/CodeGen/AMDGPU/read_register.ll
+++ b/test/CodeGen/AMDGPU/read_register.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s
 
 declare i32 @llvm.read_register.i32(metadata) #0
 declare i64 @llvm.read_register.i64(metadata) #0
@@ -8,7 +8,7 @@ declare i64 @llvm.read_register.i64(metadata) #0
 ; CHECK: s_mov_b32 m0, -1
 ; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], [[COPY_M0]]
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[COPY]]
+; CHECK: buffer_store_dword [[COPY]]
 define amdgpu_kernel void @test_read_m0(i32 addrspace(1)* %out) #0 {
   store volatile i32 0, i32 addrspace(3)* undef
   %m0 = call i32 @llvm.read_register.i32(metadata !0)
@@ -19,7 +19,7 @@ define amdgpu_kernel void @test_read_m0(i32 addrspace(1)* %out) #0 {
 ; CHECK-LABEL: {{^}}test_read_exec:
 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo
 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi
-; CHECK: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
 define amdgpu_kernel void @test_read_exec(i64 addrspace(1)* %out) #0 {
   %exec = call i64 @llvm.read_register.i64(metadata !1)
   store i64 %exec, i64 addrspace(1)* %out
@@ -29,7 +29,7 @@ define amdgpu_kernel void @test_read_exec(i64 addrspace(1)* %out) #0 {
 ; CHECK-LABEL: {{^}}test_read_flat_scratch:
 ; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], flat_scratch_lo
 ; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], flat_scratch_hi
-; CHECK: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
+; CHECK: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
 define amdgpu_kernel void @test_read_flat_scratch(i64 addrspace(1)* %out) #0 {
   %flat_scratch = call i64 @llvm.read_register.i64(metadata !2)
   store i64 %flat_scratch, i64 addrspace(1)* %out
@@ -38,7 +38,7 @@ define amdgpu_kernel void @test_read_flat_scratch(i64 addrspace(1)* %out) #0 {
 
 ; CHECK-LABEL: {{^}}test_read_flat_scratch_lo:
 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_lo
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[COPY]]
+; CHECK: buffer_store_dword [[COPY]]
 define amdgpu_kernel void @test_read_flat_scratch_lo(i32 addrspace(1)* %out) #0 {
   %flat_scratch_lo = call i32 @llvm.read_register.i32(metadata !3)
   store i32 %flat_scratch_lo, i32 addrspace(1)* %out
@@ -47,7 +47,7 @@ define amdgpu_kernel void @test_read_flat_scratch_lo(i32 addrspace(1)* %out) #0
 
 ; CHECK-LABEL: {{^}}test_read_flat_scratch_hi:
 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_hi
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[COPY]]
+; CHECK: buffer_store_dword [[COPY]]
 define amdgpu_kernel void @test_read_flat_scratch_hi(i32 addrspace(1)* %out) #0 {
   %flat_scratch_hi = call i32 @llvm.read_register.i32(metadata !4)
   store i32 %flat_scratch_hi, i32 addrspace(1)* %out
@@ -56,7 +56,7 @@ define amdgpu_kernel void @test_read_flat_scratch_hi(i32 addrspace(1)* %out) #0
 
 ; CHECK-LABEL: {{^}}test_read_exec_lo:
 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[COPY]]
+; CHECK: buffer_store_dword [[COPY]]
 define amdgpu_kernel void @test_read_exec_lo(i32 addrspace(1)* %out) #0 {
   %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
   store i32 %exec_lo, i32 addrspace(1)* %out
@@ -65,7 +65,7 @@ define amdgpu_kernel void @test_read_exec_lo(i32 addrspace(1)* %out) #0 {
 
 ; CHECK-LABEL: {{^}}test_read_exec_hi:
 ; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
-; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[COPY]]
+; CHECK: buffer_store_dword [[COPY]]
 define amdgpu_kernel void @test_read_exec_hi(i32 addrspace(1)* %out) #0 {
   %exec_hi = call i32 @llvm.read_register.i32(metadata !6)
   store i32 %exec_hi, i32 addrspace(1)* %out