]> granicus.if.org Git - llvm/commitdiff
[SimplifyDemandedBits] Use APInt::intersects to instead of ANDing and comparing to...
authorCraig Topper <craig.topper@intel.com>
Tue, 17 Sep 2019 18:19:02 +0000 (18:19 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 17 Sep 2019 18:19:02 +0000 (18:19 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372158 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/TargetLowering.cpp

index 41b3ba1733dd9736a4a18018b82315933bfe6587..cd7f64efa750c9007570f29c4dc2608d2db89baa 100644 (file)
@@ -1285,7 +1285,7 @@ bool TargetLowering::SimplifyDemandedBits(
       // out) are never demanded.
       // TODO - support non-uniform vector amounts.
       if (Op0.getOpcode() == ISD::SRL) {
-        if ((DemandedBits & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
+        if (!DemandedBits.intersects(APInt::getLowBitsSet(BitWidth, ShAmt))) {
           if (ConstantSDNode *SA2 =
                   isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
             if (SA2->getAPIntValue().ult(BitWidth)) {
@@ -1392,7 +1392,8 @@ bool TargetLowering::SimplifyDemandedBits(
       if (Op0.getOpcode() == ISD::SHL) {
         if (ConstantSDNode *SA2 =
                 isConstOrConstSplat(Op0.getOperand(1), DemandedElts)) {
-          if ((DemandedBits & APInt::getHighBitsSet(BitWidth, ShAmt)) == 0) {
+          if (!DemandedBits.intersects(
+                  APInt::getHighBitsSet(BitWidth, ShAmt))) {
             if (SA2->getAPIntValue().ult(BitWidth)) {
               unsigned C1 = SA2->getZExtValue();
               unsigned Opc = ISD::SRL;