[X86] Add an extra instruction to TruncAssertSext.ll to prevent the 'or' from being...

If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose.

While here regenerate the test with update_llc_test_checks.py

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312995 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/TruncAssertSext.ll b/test/CodeGen/X86/TruncAssertSext.ll
index 3d92cb045ae76dee3aa03db98d23e8b879feed71..d4f9a5d4873ceffac216928df41d46482eec9f08 100644 (file)
--- a/test/CodeGen/X86/TruncAssertSext.ll
+++ b/test/CodeGen/X86/TruncAssertSext.ll
@@ -1,16 +1,20 @@
-; RUN: llc < %s -O2 -mtriple=x86_64-- | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -O2 -mtriple=x86_64-unknown-unknown | FileCheck %s
 ; Checks that a zeroing mov is inserted for the trunc/zext pair even when
 ; the source of the zext is an AssertSext node
 ; PR20494
 
 define i64 @main(i64 %a) {
-; CHECK-LABEL: main
-; CHECK: movl %e{{..}}, %eax
-; CHECK: ret
+; CHECK-LABEL: main:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    orq $-2, %rdi
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    retq
   %or = or i64 %a, -2
   %trunc = trunc i64 %or to i32
   br label %l
 l:
   %ext = zext i32 %trunc to i64
+  trunc i64 %or to i32 ; to keep the or from being narrowed
   ret i64 %ext
 }