Nope, I'm wrong. It looks like someone else removed these on purpose and

it just happened to break the bot right when I did my push. So I'm undoing
this mornings incorrect push. I've also kicked off an email to hopefully
get the bot fixed the correct way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374049 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/ProgrammingDocumentation.rst b/docs/ProgrammingDocumentation.rst
deleted file mode 100644 (file)
index fa8f114..0000000
--- a/docs/ProgrammingDocumentation.rst
+++ /dev/null
@@ -1,54 +0,0 @@
-Programming Documentation\r
-=========================\r
-\r
-For developers of applications which use LLVM as a library.\r
-\r
-.. toctree::\r
-   :hidden:\r
-\r
-   Atomics\r
-   CommandLine\r
-   ExtendingLLVM\r
-   HowToSetUpLLVMStyleRTTI\r
-   ProgrammersManual\r
-   Extensions\r
-   LibFuzzer\r
-   FuzzingLLVM\r
-   ScudoHardenedAllocator\r
-   OptBisect\r
-   GwpAsan\r
-\r
-:doc:`Atomics`\r
-  Information about LLVM's concurrency model.\r
-\r
-:doc:`ProgrammersManual`\r
-  Introduction to the general layout of the LLVM sourcebase, important classes\r
-  and APIs, and some tips & tricks.\r
-\r
-:doc:`Extensions`\r
-  LLVM-specific extensions to tools and formats LLVM seeks compatibility with.\r
-\r
-:doc:`CommandLine`\r
-  Provides information on using the command line parsing library.\r
-\r
-:doc:`HowToSetUpLLVMStyleRTTI`\r
-  How to make ``isa<>``, ``dyn_cast<>``, etc. available for clients of your\r
-  class hierarchy.\r
-\r
-:doc:`ExtendingLLVM`\r
-  Look here to see how to add instructions and intrinsics to LLVM.\r
-\r
-:doc:`LibFuzzer`\r
-  A library for writing in-process guided fuzzers.\r
-\r
-:doc:`FuzzingLLVM`\r
-  Information on writing and using Fuzzers to find bugs in LLVM.\r
-\r
-:doc:`ScudoHardenedAllocator`\r
-  A library that implements a security-hardened `malloc()`.\r
-\r
-:doc:`OptBisect`\r
-  A command line option for debugging optimization-induced failures.\r
-\r
-:doc:`GwpAsan`\r
-  A sampled heap memory error detection toolkit designed for production use.
\ No newline at end of file

diff --git a/docs/SubsystemDocumentation.rst b/docs/SubsystemDocumentation.rst
deleted file mode 100644 (file)
index cac0ce8..0000000
--- a/docs/SubsystemDocumentation.rst
+++ /dev/null
@@ -1,206 +0,0 @@
-.. _index-subsystem-docs:\r
-\r
-Subsystem Documentation\r
-=======================\r
-\r
-For API clients and LLVM developers.\r
-\r
-.. toctree::\r
-   :hidden:\r
-\r
-   AliasAnalysis\r
-   MemorySSA\r
-   BitCodeFormat\r
-   BlockFrequencyTerminology\r
-   BranchWeightMetadata\r
-   Bugpoint\r
-   CodeGenerator\r
-   ExceptionHandling\r
-   AddingConstrainedIntrinsics\r
-   LinkTimeOptimization\r
-   SegmentedStacks\r
-   TableGenFundamentals\r
-   TableGen/index\r
-   DebuggingJITedCode\r
-   GoldPlugin\r
-   MarkedUpDisassembly\r
-   SystemLibrary\r
-   SupportLibrary\r
-   SourceLevelDebugging\r
-   Vectorizers\r
-   WritingAnLLVMBackend\r
-   GarbageCollection\r
-   WritingAnLLVMPass\r
-   HowToUseAttributes\r
-   NVPTXUsage\r
-   AMDGPUUsage\r
-   StackMaps\r
-   InAlloca\r
-   BigEndianNEON\r
-   CoverageMappingFormat\r
-   Statepoints\r
-   MergeFunctions\r
-   TypeMetadata\r
-   TransformMetadata\r
-   FaultMaps\r
-   Coroutines\r
-   GlobalISel\r
-   XRay\r
-   XRayExample\r
-   XRayFDRFormat\r
-   PDB/index\r
-   CFIVerify\r
-   SpeculativeLoadHardening\r
-   StackSafetyAnalysis\r
-   LoopTerminology\r
-   DependenceGraphs/index\r
-\r
-:doc:`WritingAnLLVMPass`\r
-   Information on how to write LLVM transformations and analyses.\r
-\r
-:doc:`WritingAnLLVMBackend`\r
-   Information on how to write LLVM backends for machine targets.\r
-\r
-:doc:`CodeGenerator`\r
-   The design and implementation of the LLVM code generator.  Useful if you are\r
-   working on retargetting LLVM to a new architecture, designing a new codegen\r
-   pass, or enhancing existing components.\r
-\r
-:doc:`TableGen <TableGen/index>`\r
-   Describes the TableGen tool, which is used heavily by the LLVM code\r
-   generator.\r
-\r
-:doc:`AliasAnalysis`\r
-   Information on how to write a new alias analysis implementation or how to\r
-   use existing analyses.\r
-\r
-:doc:`MemorySSA`\r
-   Information about the MemorySSA utility in LLVM, as well as how to use it.\r
-\r
-:doc:`GarbageCollection`\r
-   The interfaces source-language compilers should use for compiling GC'd\r
-   programs.\r
-\r
-:doc:`Source Level Debugging with LLVM <SourceLevelDebugging>`\r
-   This document describes the design and philosophy behind the LLVM\r
-   source-level debugger.\r
-\r
-:doc:`Vectorizers`\r
-   This document describes the current status of vectorization in LLVM.\r
-\r
-:doc:`ExceptionHandling`\r
-   This document describes the design and implementation of exception handling\r
-   in LLVM.\r
-\r
-:doc:`AddingConstrainedIntrinsics`\r
-   Gives the steps necessary when adding a new constrained math intrinsic\r
-   to LLVM.\r
-\r
-:doc:`Bugpoint`\r
-   Automatic bug finder and test-case reducer description and usage\r
-   information.\r
-\r
-:doc:`BitCodeFormat`\r
-   This describes the file format and encoding used for LLVM "bc" files.\r
-\r
-:doc:`Support Library <SupportLibrary>`\r
-   This document describes the LLVM Support Library (``lib/Support``) and\r
-   how to keep LLVM source code portable\r
-\r
-:doc:`LinkTimeOptimization`\r
-   This document describes the interface between LLVM intermodular optimizer\r
-   and the linker and its design\r
-\r
-:doc:`GoldPlugin`\r
-   How to build your programs with link-time optimization on Linux.\r
-\r
-:doc:`DebuggingJITedCode`\r
-   How to debug JITed code with GDB.\r
-\r
-:doc:`MCJITDesignAndImplementation`\r
-   Describes the inner workings of MCJIT execution engine.\r
-\r
-:doc:`ORCv2`\r
-   Describes the design and implementation of the ORC APIs, including some\r
-   usage examples, and a guide for users transitioning from ORCv1 to ORCv2.\r
-\r
-:doc:`BranchWeightMetadata`\r
-   Provides information about Branch Prediction Information.\r
-\r
-:doc:`BlockFrequencyTerminology`\r
-   Provides information about terminology used in the ``BlockFrequencyInfo``\r
-   analysis pass.\r
-\r
-:doc:`SegmentedStacks`\r
-   This document describes segmented stacks and how they are used in LLVM.\r
-\r
-:doc:`MarkedUpDisassembly`\r
-   This document describes the optional rich disassembly output syntax.\r
-\r
-:doc:`HowToUseAttributes`\r
-  Answers some questions about the new Attributes infrastructure.\r
-\r
-:doc:`NVPTXUsage`\r
-   This document describes using the NVPTX backend to compile GPU kernels.\r
-\r
-:doc:`AMDGPUUsage`\r
-   This document describes using the AMDGPU backend to compile GPU kernels.\r
-\r
-:doc:`StackMaps`\r
-  LLVM support for mapping instruction addresses to the location of\r
-  values and allowing code to be patched.\r
-\r
-:doc:`BigEndianNEON`\r
-  LLVM's support for generating NEON instructions on big endian ARM targets is\r
-  somewhat nonintuitive. This document explains the implementation and rationale.\r
-\r
-:doc:`CoverageMappingFormat`\r
-  This describes the format and encoding used for LLVM’s code coverage mapping.\r
-\r
-:doc:`Statepoints`\r
-  This describes a set of experimental extensions for garbage\r
-  collection support.\r
-\r
-:doc:`MergeFunctions`\r
-  Describes functions merging optimization.\r
-\r
-:doc:`InAlloca`\r
-  Description of the ``inalloca`` argument attribute.\r
-\r
-:doc:`FaultMaps`\r
-  LLVM support for folding control flow into faulting machine instructions.\r
-\r
-:doc:`CompileCudaWithLLVM`\r
-  LLVM support for CUDA.\r
-\r
-:doc:`Coroutines`\r
-  LLVM support for coroutines.\r
-\r
-:doc:`GlobalISel`\r
-  This describes the prototype instruction selection replacement, GlobalISel.\r
-\r
-:doc:`XRay`\r
-  High-level documentation of how to use XRay in LLVM.\r
-\r
-:doc:`XRayExample`\r
-  An example of how to debug an application with XRay.\r
-\r
-:doc:`The Microsoft PDB File Format <PDB/index>`\r
-  A detailed description of the Microsoft PDB (Program Database) file format.\r
-\r
-:doc:`CFIVerify`\r
-  A description of the verification tool for Control Flow Integrity.\r
-\r
-:doc:`SpeculativeLoadHardening`\r
-  A description of the Speculative Load Hardening mitigation for Spectre v1.\r
-\r
-:doc:`StackSafetyAnalysis`\r
-  This document describes the design of the stack safety analysis of local\r
-  variables.\r
-\r
-:doc:`LoopTerminology`\r
-  A document describing Loops and associated terms as used in LLVM.\r
-\r
-:doc:`Dependence Graphs <DependenceGraphs/index>`\r
-  A description of the design of the various dependence graphs such as\r
-  the DDG (Data Dependence Graph).\r