[x86] regenerate checks; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296881 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/peep-setb.ll b/test/CodeGen/X86/peep-setb.ll
index adae8acd0432b2fe7c4f8df5621751d1c9adf2fd..c8a97f7dff194463316e81758c206eec27767fab 100644 (file)
--- a/test/CodeGen/X86/peep-setb.ll
+++ b/test/CodeGen/X86/peep-setb.ll
@@ -1,82 +1,120 @@
-; RUN: llc -march=x86-64 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
 
 define i8 @test1(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpb %sil, %dil
+; CHECK-NEXT:    adcb $0, %sil
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i8 %a, %b
   %cond = zext i1 %cmp to i8
   %add = add i8 %cond, %b
   ret i8 %add
-; CHECK-LABEL: test1:
-; CHECK: adcb $0
 }
 
 define i32 @test2(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    adcl $0, %esi
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i32 %a, %b
   %cond = zext i1 %cmp to i32
   %add = add i32 %cond, %b
   ret i32 %add
-; CHECK-LABEL: test2:
-; CHECK: adcl $0
 }
 
 define i64 @test3(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    adcq $0, %rsi
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i64 %a, %b
   %conv = zext i1 %cmp to i64
   %add = add i64 %conv, %b
   ret i64 %add
-; CHECK-LABEL: test3:
-; CHECK: adcq $0
 }
 
 define i8 @test4(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpb %sil, %dil
+; CHECK-NEXT:    sbbb $0, %sil
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i8 %a, %b
   %cond = zext i1 %cmp to i8
   %sub = sub i8 %b, %cond
   ret i8 %sub
-; CHECK-LABEL: test4:
-; CHECK: sbbb $0
 }
 
 define i32 @test5(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: test5:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    sbbl $0, %esi
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i32 %a, %b
   %cond = zext i1 %cmp to i32
   %sub = sub i32 %b, %cond
   ret i32 %sub
-; CHECK-LABEL: test5:
-; CHECK: sbbl $0
 }
 
 define i64 @test6(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: test6:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    sbbq $0, %rsi
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i64 %a, %b
   %conv = zext i1 %cmp to i64
   %sub = sub i64 %b, %conv
   ret i64 %sub
-; CHECK-LABEL: test6:
-; CHECK: sbbq $0
 }
 
 define i8 @test7(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: test7:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpb %sil, %dil
+; CHECK-NEXT:    adcb $0, %sil
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i8 %a, %b
   %cond = sext i1 %cmp to i8
   %sub = sub i8 %b, %cond
   ret i8 %sub
-; CHECK-LABEL: test7:
-; CHECK: adcb $0
 }
 
 define i32 @test8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: test8:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    adcl $0, %esi
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i32 %a, %b
   %cond = sext i1 %cmp to i32
   %sub = sub i32 %b, %cond
   ret i32 %sub
-; CHECK-LABEL: test8:
-; CHECK: adcl $0
 }
 
 define i64 @test9(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: test9:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    adcq $0, %rsi
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    retq
   %cmp = icmp ult i64 %a, %b
   %conv = sext i1 %cmp to i64
   %sub = sub i64 %b, %conv
   ret i64 %sub
-; CHECK-LABEL: test9:
-; CHECK: adcq $0
 }
+