[PowerPC] make tests immune to improved undef handling

The fma mutate test will not exercise what it was intended to test
once we simplify those ops immediately, but the test will still
pass with the existing CHECKs, so I'm leaving it in case that
still has minimal value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373149 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/PowerPC/pr38087.ll b/test/CodeGen/PowerPC/pr38087.ll
index 2736ffa723c1a8d6d3da6d3021b742353a46e737..2ef4c689beab7f166246aaa197dc9c30f0f3c91f 100644 (file)
--- a/test/CodeGen/PowerPC/pr38087.ll
+++ b/test/CodeGen/PowerPC/pr38087.ll
@@ -8,16 +8,16 @@ declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #
 ; Function Attrs: nounwind readnone speculatable
 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #0
 
-define void @draw_llvm_vs_variant0() {
+define void @draw_llvm_vs_variant0(<4 x float> %x) {
 ; CHECK-LABEL: draw_llvm_vs_variant0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfd f0, 0(r3)
-; CHECK-NEXT:    xxpermdi v2, f0, f0, 2
-; CHECK-NEXT:    vmrglh v2, v2, v2
-; CHECK-NEXT:    vextsh2w v2, v2
-; CHECK-NEXT:    xvcvsxwsp vs0, v2
+; CHECK-NEXT:    xxpermdi v3, f0, f0, 2
+; CHECK-NEXT:    vmrglh v3, v3, v3
+; CHECK-NEXT:    vextsh2w v3, v3
+; CHECK-NEXT:    xvcvsxwsp vs0, v3
 ; CHECK-NEXT:    xxspltw vs0, vs0, 2
-; CHECK-NEXT:    xvmaddasp vs0, vs0, vs0
+; CHECK-NEXT:    xvmaddasp vs0, v2, v2
 ; CHECK-NEXT:    stxvx vs0, 0, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -49,7 +49,7 @@ entry:
   %24 = and <4 x i32> %23, %22
   %25 = bitcast <4 x i32> %24 to <4 x float>
   %26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
-  %27 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> undef, <4 x float> %26)
+  %27 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> %x, <4 x float> %26)
   store <4 x float> %27, <4 x float>* undef
   ret void
 }

diff --git a/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
index ed6b49dd7f8b86eb754124ee98cbe733f14b75e9..301446a9ee14c2d32775d1185c67380c38c6629c 100644 (file)
--- a/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
+++ b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
@@ -3,12 +3,12 @@ target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
-define void @acosh_float8(<4 x i32> %v1, <4 x i32> %v2) #0 {
+define void @acosh_float8(<4 x i32> %v1, <4 x i32> %v2, <4 x float> %x) #0 {
 entry:
   br i1 undef, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> <float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000>, <4 x float> undef) #0
+  %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> <float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000>, <4 x float> %x) #0
   %astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32>
   %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, %v1
   %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, %v2