Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: arsenm, dschuff, jyknight, sdardis, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375398
91177308-0d34-0410-b5e6-
96231b3b80d8
private:
StackDirection StackDir;
Align StackAlignment;
- unsigned TransientStackAlignment;
+ Align TransientStackAlignment;
int LocalAreaOffset;
bool StackRealignable;
public:
TargetFrameLowering(StackDirection D, Align StackAl, int LAO,
- unsigned TransAl = 1, bool StackReal = true)
+ Align TransAl = Align::None(), bool StackReal = true)
: StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl),
LocalAreaOffset(LAO), StackRealignable(StackReal) {}
/// calls.
///
unsigned getTransientStackAlignment() const {
- return TransientStackAlignment;
+ return TransientStackAlignment.value();
}
/// isStackRealignable - This method returns whether the stack can be
case ICmpInst::ICMP_UGE:
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
- case ICmpInst::ICMP_ULE: {
+ case ICmpInst::ICMP_ULE: {
// If operand >=s 0 then ZExt == SExt. If operand <s 0 then ZExt <u SExt.
const SCEVZeroExtendExpr *ZExt = dyn_cast<SCEVZeroExtendExpr>(LHS);
const SCEVSignExtendExpr *SExt = dyn_cast<SCEVSignExtendExpr>(RHS);
class AArch64FrameLowering : public TargetFrameLowering {
public:
explicit AArch64FrameLowering()
- : TargetFrameLowering(StackGrowsDown, Align(16), 0, 16,
+ : TargetFrameLowering(StackGrowsDown, Align(16), 0, Align(16),
true /*StackRealignable*/) {}
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
using namespace llvm;
AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, Align StackAl,
- int LAO, unsigned TransAl)
+ int LAO, Align TransAl)
: TargetFrameLowering(D, StackAl, LAO, TransAl) {}
AMDGPUFrameLowering::~AMDGPUFrameLowering() = default;
class AMDGPUFrameLowering : public TargetFrameLowering {
public:
AMDGPUFrameLowering(StackDirection D, Align StackAl, int LAO,
- unsigned TransAl = 1);
+ Align TransAl = Align::None());
~AMDGPUFrameLowering() override;
/// \returns The number of 32-bit sub-registers that are used when storing
class R600FrameLowering : public AMDGPUFrameLowering {
public:
R600FrameLowering(StackDirection D, Align StackAl, int LAO,
- unsigned TransAl = 1)
+ Align TransAl = Align::None())
: AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
~R600FrameLowering() override;
class SIFrameLowering final : public AMDGPUFrameLowering {
public:
SIFrameLowering(StackDirection D, Align StackAl, int LAO,
- unsigned TransAl = 1)
+ Align TransAl = Align::None())
: AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
~SIFrameLowering() override = default;
unsigned NumAlignedDPRCS2Regs);
ARMFrameLowering::ARMFrameLowering(const ARMSubtarget &sti)
- : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
+ : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, Align(4)),
STI(sti) {}
bool ARMFrameLowering::keepFramePointer(const MachineFunction &MF) const {
class HexagonFrameLowering : public TargetFrameLowering {
public:
explicit HexagonFrameLowering()
- : TargetFrameLowering(StackGrowsDown, Align(8), 0, 1, true) {}
+ : TargetFrameLowering(StackGrowsDown, Align(8), 0, Align::None(), true) {}
// All of the prolog/epilog functionality, including saving and restoring
// callee-saved registers is handled in emitPrologue. This is to have the
public:
explicit MSP430FrameLowering()
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(2), -2,
- 2) {}
+ Align(2)) {}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
public:
explicit MipsFrameLowering(const MipsSubtarget &sti, Align Alignment)
- : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment.value()),
- STI(sti) {}
+ : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {
+ }
static const MipsFrameLowering *create(const MipsSubtarget &ST);
SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
ST.is64Bit() ? Align(16) : Align(8), 0,
- ST.is64Bit() ? 16 : 8) {}
+ ST.is64Bit() ? Align(16) : Align(8)) {}
void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
MachineBasicBlock &MBB,
SystemZFrameLowering::SystemZFrameLowering()
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(8),
- -SystemZMC::CallFrameSize, 8,
+ -SystemZMC::CallFrameSize, Align(8),
false /* StackRealignable */) {
// Create a mapping from register number to save slot offset.
RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
WebAssemblyFrameLowering()
: TargetFrameLowering(StackGrowsDown, /*StackAlignment=*/Align(16),
/*LocalAreaOffset=*/0,
- /*TransientStackAlignment=*/16,
+ /*TransientStackAlignment=*/Align(16),
/*StackRealignable=*/true) {}
MachineBasicBlock::iterator