[Hexagon] Stop pmpy recognition when shift conversion fails

The conversion of shifts from right shifts to left shifts may fail.
In such case, the pmpy recognition cannot proceed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305289 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
index b748b58bc0ae38d70fd0a170a55b16e3d1213888..f82ad6cb3da6ad8b9a598f5bfdec2091202535ec 100644 (file)
--- a/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
+++ b/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
@@ -1744,7 +1744,8 @@ bool PolynomialMultiplyRecognize::recognize() {
     // wide as the target's pmpy instruction.
     if (!promoteTypes(LoopB, ExitB))
       return false;
-    convertShiftsToLeft(LoopB, ExitB, IterCount);
+    if (!convertShiftsToLeft(LoopB, ExitB, IterCount))
+      return false;
     cleanupLoopBody(LoopB);
   }
 

diff --git a/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll b/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
new file mode 100644 (file)
index 0000000..0abf8f8
--- /dev/null
+++ b/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
@@ -0,0 +1,48 @@
+; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
+; REQUIRES: asserts
+;
+; Check for sane output, this used to crash.
+; CHECK: define void @fred
+
+; The conversion of shifts from right to left failed, but the return
+; code was not checked and the transformation proceeded.
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+@A = common global [256 x i32] zeroinitializer, align 8
+
+; Function Attrs: noinline nounwind
+define void @fred() local_unnamed_addr #0 {
+b0:
+  br label %b1
+
+b1:                                               ; preds = %b13, %b0
+  %v2 = phi i32 [ 0, %b0 ], [ %v16, %b13 ]
+  br label %b3
+
+b3:                                               ; preds = %b3, %b1
+  %v4 = phi i32 [ %v2, %b1 ], [ %v10, %b3 ]
+  %v5 = phi i32 [ 0, %b1 ], [ %v11, %b3 ]
+  %v6 = and i32 %v4, 1
+  %v7 = icmp ne i32 %v6, 0
+  %v8 = lshr i32 %v4, 1
+  %v9 = xor i32 %v8, 123456789
+  %v10 = select i1 %v7, i32 %v9, i32 %v8
+  %v11 = add nuw nsw i32 %v5, 1
+  %v12 = icmp ne i32 %v11, 8
+  br i1 %v12, label %b3, label %b13
+
+b13:                                              ; preds = %b3
+  %v14 = phi i32 [ %v10, %b3 ]
+  %v15 = getelementptr inbounds [256 x i32], [256 x i32]* @A, i32 0, i32 %v2
+  store i32 %v14, i32* %v15, align 4
+  %v16 = add nuw nsw i32 %v2, 1
+  %v17 = icmp ne i32 %v16, 256
+  br i1 %v17, label %b1, label %b18
+
+b18:                                              ; preds = %b13
+  ret void
+}
+
+attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" }