[ARM] Correct handling of LSL #0 in an IT block

The check for LSL #0 in an IT block was checking if operand 4 was zero, but
operand 4 is the condition code operand so it was actually checking for LSLEQ.
Fix this by checking operand 3, which really is the immediate operand, and add
some tests.

Differential Revision: https://reviews.llvm.org/D30692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297142 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index de3b51ca5c7873cc4a44faeba15d54b4a826e9fd..f20ee1b91ac136690c94857e394fc4229a12a21f 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8940,7 +8940,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
         inITBlock())
       return Match_RequiresNotITBlock;
     // LSL with zero immediate is not allowed in an IT block
-    if (Opc == ARM::tLSLri && Inst.getOperand(4).getImm() == 0 && inITBlock())
+    if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
       return Match_RequiresNotITBlock;
   } else if (isThumbOne()) {
     // Some high-register supporting Thumb1 encodings only allow both registers

diff --git a/test/MC/ARM/lsl-zero.s b/test/MC/ARM/lsl-zero.s
index 6fa7a73d632d0ff1fb105fe3dd7c8c5a8ece13bd..02d094c8521906c44f5cb425c445adb30938815c 100644 (file)
--- a/test/MC/ARM/lsl-zero.s
+++ b/test/MC/ARM/lsl-zero.s
@@ -122,19 +122,33 @@
         itt eq
         lsleq  r0, r1, #0
         lslseq r0, r1, #0
+        itt gt
+        lslgt  r0, r1, #0
+        lslsgt r0, r1, #0
 
 // CHECK-NONARM: moveq.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
 // CHECK-NONARM: movseq.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
+// CHECK-NONARM: movgt.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
+// CHECK-NONARM: movsgt.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
 
 // CHECK-ARM: moveq r0, r1              @ encoding: [0x01,0x00,0xa0,0x01]
 // CHECK-ARM: movseq r0, r1             @ encoding: [0x01,0x00,0xb0,0x01]
+// CHECK-ARM: movgt r0, r1              @ encoding: [0x01,0x00,0xa0,0xc1]
+// CHECK-ARM: movsgt r0, r1             @ encoding: [0x01,0x00,0xb0,0xc1]
 
         itt eq
         moveq  r0, r1, lsl #0
         movseq r0, r1, lsl #0
+        itt gt
+        movgt  r0, r1, lsl #0
+        movsgt r0, r1, lsl #0
 
 // CHECK-NONARM: moveq.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
 // CHECK-NONARM: movseq.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
+// CHECK-NONARM: movgt.w r0, r1         @ encoding: [0x4f,0xea,0x01,0x00]
+// CHECK-NONARM: movsgt.w r0, r1        @ encoding: [0x5f,0xea,0x01,0x00]
 
 // CHECK-ARM: moveq r0, r1              @ encoding: [0x01,0x00,0xa0,0x01]
 // CHECK-ARM: movseq r0, r1             @ encoding: [0x01,0x00,0xb0,0x01]
+// CHECK-ARM: movgt r0, r1              @ encoding: [0x01,0x00,0xa0,0xc1]
+// CHECK-ARM: movsgt r0, r1             @ encoding: [0x01,0x00,0xb0,0xc1]