]> granicus.if.org Git - llvm/commitdiff
[AMDGPU] Fix SI scheduler LiveOut Refcount issue
authorValery Pykhtin <Valery.Pykhtin@amd.com>
Mon, 27 Mar 2017 17:06:36 +0000 (17:06 +0000)
committerValery Pykhtin <Valery.Pykhtin@amd.com>
Mon, 27 Mar 2017 17:06:36 +0000 (17:06 +0000)
Patch by Axel Davy (axel.davy@normalesup.org)

Differential revision: https://reviews.llvm.org/D30145

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298857 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AMDGPU/SIMachineScheduler.cpp
lib/Target/AMDGPU/SIMachineScheduler.h

index b6883bfb7dfd349e213cb7b1814dedbbef4536b1..2e8e8ebc629b55ec3582b0fbc8db2ebe86af048e 100644 (file)
@@ -1350,6 +1350,24 @@ SIScheduleBlockScheduler::SIScheduleBlockScheduler(SIScheduleDAGMI *DAG,
   std::set<unsigned> InRegs = DAG->getInRegs();
   addLiveRegs(InRegs);
 
+  // Increase LiveOutRegsNumUsages for blocks
+  // producing registers consumed in another
+  // scheduling region.
+  for (unsigned Reg : DAG->getOutRegs()) {
+    for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
+      // Do reverse traversal
+      int ID = BlocksStruct.TopDownIndex2Block[Blocks.size()-1-i];
+      SIScheduleBlock *Block = Blocks[ID];
+      const std::set<unsigned> &OutRegs = Block->getOutRegs();
+
+      if (OutRegs.find(Reg) == OutRegs.end())
+        continue;
+
+      ++LiveOutRegsNumUsages[ID][Reg];
+      break;
+    }
+  }
+
   // Fill LiveRegsConsumers for regs that were already
   // defined before scheduling.
   for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
index 2dc4b346de7921ab8760f1c8cfa8fd67d8774842..6978b83910d030ea1a4bdf6d335d295fab36da72 100644 (file)
@@ -467,6 +467,14 @@ public:
     return InRegs;
   }
 
+  std::set<unsigned> getOutRegs() {
+    std::set<unsigned> OutRegs;
+    for (const auto &RegMaskPair : RPTracker.getPressure().LiveOutRegs) {
+      OutRegs.insert(RegMaskPair.RegUnit);
+    }
+    return OutRegs;
+  };
+
   unsigned getVGPRSetID() const { return VGPRSetID; }
   unsigned getSGPRSetID() const { return SGPRSetID; }