*
*
* IDENTIFICATION
- * $Header: /cvsroot/pgsql/src/backend/storage/buffer/Attic/s_lock.c,v 1.29 2001/01/14 05:08:15 tgl Exp $
+ * $Header: /cvsroot/pgsql/src/backend/storage/buffer/Attic/s_lock.c,v 1.30 2001/01/19 20:39:16 momjian Exp $
*
*-------------------------------------------------------------------------
*/
}
}
-
-
-
/*
* Various TAS implementations that cannot live in s_lock.h as no inline
* definition exists (yet).
tas_dummy() /* really means: extern int tas(slock_t
* **lock); */
{
- __asm__(" \n\
-.global _tas \n\
-_tas: \n\
- movel sp@(0x4),a0 \n\
- tas a0@ \n\
- beq _success \n\
- moveq #-128,d0 \n\
- rts \n\
-_success: \n\
- moveq #0,d0 \n\
- rts \n\
- ");
+ __asm__ __volatile__(
+"\
+.global _tas \n\
+_tas: \n\
+ movel sp@(0x4),a0 \n\
+ tas a0@ \n\
+ beq _success \n\
+ moveq #-128,d0 \n\
+ rts \n\
+_success: \n\
+ moveq #0,d0 \n\
+ rts");
}
#endif /* __m68k__ */
static void
tas_dummy()
{
- __asm__(" \n\
- .globl tas \n\
- .globl _tas \n\
-_tas: \n\
-tas: \n\
- lwarx r5,0,r3 \n\
- cmpwi r5,0 \n\
- bne fail \n\
- addi r5,r5,1 \n\
- stwcx. r5,0,r3 \n\
- beq success \n\
-fail: li r3,1 \n\
- blr \n\
-success: \n\
- li r3,0 \n\
- blr \n\
+ __asm__ __volatile__(
+"\
+ .globl tas \n\
+ .globl _tas \n\
+_tas: \n\
+tas: \n\
+ lwarx r5,0,r3 \n\
+ cmpwi r5,0 \n\
+ bne fail \n\
+ addi r5,r5,1 \n\
+ stwcx. r5,0,r3 \n\
+ beq success \n\
+fail: li r3,1 \n\
+ blr \n\
+success: \n\
+ li r3,0 \n\
+ blr \n\
");
}
static void
tas_dummy()
{
- __asm__(" \n\
-.global tas \n\
-tas: \n\
- lwarx 5,0,3 \n\
- cmpwi 5,0 \n\
- bne fail \n\
- addi 5,5,1 \n\
- stwcx. 5,0,3 \n\
- beq success \n\
-fail: li 3,1 \n\
- blr \n\
-success: \n\
- li 3,0 \n\
- blr \n\
- ");
+ __asm__ __volatile__(
+"\
+.global tas \n\
+tas: \n\
+ lwarx 5,0,3 \n\
+ cmpwi 5,0 \n\
+ bne fail \n\
+ addi 5,5,1 \n\
+ stwcx. 5,0,3 \n\
+ beq success \n\
+fail: li 3,1 \n\
+ blr \n\
+success: \n\
+ li 3,0 \n\
+ blr");
}
#endif /* __powerpc__ */
static void
tas_dummy()
{
- __asm__(" \n\
-.global tas \n\
-tas: \n\
- .frame $sp, 0, $31 \n\
- ll $14, 0($4) \n\
- or $15, $14, 1 \n\
- sc $15, 0($4) \n\
- beq $15, 0, fail \n\
- bne $14, 0, fail \n\
- li $2, 0 \n\
- .livereg 0x2000FF0E,0x00000FFF \n\
- j $31 \n\
-fail: \n\
- li $2, 1 \n\
- j $31 \n\
- ");
+ __asm__ _volatile__(
+"\
+.global tas \n\
+tas: \n\
+ .frame $sp, 0, $31 \n\
+ ll $14, 0($4) \n\
+ or $15, $14, 1 \n\
+ sc $15, 0($4) \n\
+ beq $15, 0, fail\n\
+ bne $14, 0, fail\n\
+ li $2, 0 \n\
+ .livereg 0x2000FF0E,0x00000FFF \n\
+ j $31 \n\
+fail: \n\
+ li $2, 1 \n\
+ j $31");
}
#endif /* __mips__ */
*
*
* IDENTIFICATION
- * $Header: /cvsroot/pgsql/src/include/storage/s_lock.h,v 1.82 2001/01/19 07:03:53 momjian Exp $
+ * $Header: /cvsroot/pgsql/src/include/storage/s_lock.h,v 1.83 2001/01/19 20:39:16 momjian Exp $
*
*-------------------------------------------------------------------------
*/
* Standard _asm format:
*
* __asm__ __volatile__(
- * "command;"
- * "command;"
- * "command;"
+ * "command \n"
+ * "command \n"
+ * "command \n"
* : "=r"(_res) return value, in register
* : "r"(lock) argument, 'lock pointer', in register
* : "r0"); inline code uses this register
register slock_t _res = 1;
__asm__ __volatile__(
- "lock;"
- "xchgb %0,%1;"
+ "lock \n"
+ "xchgb %0,%1 \n"
: "=q"(_res), "=m"(*lock)
: "0"(_res));
return (int) _res;
long int ret;
__asm__ __volatile__(
- "xchg4 %0=%1,%2;"
+ "xchg4 %0=%1,%2 \n"
: "=r"(ret), "=m"(*lock)
: "r"(1), "1"(*lock)
: "memory");
register slock_t _res = 1;
__asm__ __volatile__(
- "swpb %0, %0, [%3];"
+ "swpb %0, %0, [%3] \n"
: "=r"(_res), "=m"(*lock)
: "0"(_res), "r"(lock));
return (int) _res;
int _res;
__asm__ __volatile__(
- "la 1,1;"
- "l 2,%2;"
- "slr 0,0;"
- "cs 0,1,0(2);"
- "lr %1,0;"
+ "la 1,1 \n"
+ "l 2,%2 \n"
+ "slr 0,0 \n"
+ "cs 0,1,0(2) \n"
+ "lr %1,0 \n"
: "=m"(lock), "=d"(_res)
: "m"(lock)
: "0", "1", "2");
register slock_t _res = 1;
__asm__ __volatile__(
- "ldstub [%2], %0;"
+ "ldstub [%2], %0 \n"
: "=r"(_res), "=m"(*lock)
: "r"(lock));
return (int) _res;
register int rv;
__asm__ __volatile__(
- "tas %1;"
- "sne %0;"
+ "tas %1 \n"
+ "sne %0 \n"
: "=d"(rv), "=m"(*lock)
: "1"(*lock)
: "cc");
register _res;
__asm__ __volatile__(
- "movl $1, r0;"
- "bbssi $0, (%1), 1f;"
- "clrl r0;"
- "1: movl r0, %0;"
+ "movl $1, r0 \n"
+ "bbssi $0, (%1), 1f \n"
+ "clrl r0 \n"
+ "1: movl r0, %0 \n"
: "=r"(_res)
: "r"(lock)
: "r0");
register _res;
__asm__ __volatile__(
- "sbitb 0, %0;"
- "sfsd %1;"
+ "sbitb 0, %0 \n"
+ "sfsd %1 \n"
: "=m"(*lock), "=r"(_res));
return (int) _res;
}
register slock_t _res;
__asm__ __volatile__(
- "ldq $0, %0;"
- "bne $0, 2f;"
- "ldq_l %1, %0;"
- "bne %1, 2f;"
- "mov 1, $0;"
- "stq_c $0, %0;"
- "beq $0, 2f;"
- "mb;"
- "br 3f;"
- "2: mov 1, %1;"
+ "ldq $0, %0 \n"
+ "bne $0, 2f \n"
+ "ldq_l %1, %0 \n"
+ "bne %1, 2f \n"
+ "mov 1, $0 \n"
+ "stq_c $0, %0 \n"
+ "beq $0, 2f \n"
+ "mb \n"
+ "br 3f \n"
+ "2: mov 1, %1 \n"
"3:"
: "=m"(*lock), "=r"(_res)
: