AMDGPU/GlobalISel: Select 16-bit VALU bit ops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371807 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/VOP2Instructions.td b/lib/Target/AMDGPU/VOP2Instructions.td
index df45771e26452d8f8812ed4b61c4a53a0a6829c0..e5ca22c87f9fcd44231a9fa45d756ccfe0e90482 100644 (file)
--- a/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/lib/Target/AMDGPU/VOP2Instructions.td
@@ -798,17 +798,17 @@ defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64,   1>;
 
 def : GCNPat <
   (and i16:$src0, i16:$src1),
-  (V_AND_B32_e64 $src0, $src1)
+  (V_AND_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
 >;
 
 def : GCNPat <
   (or i16:$src0, i16:$src1),
-  (V_OR_B32_e64 $src0, $src1)
+  (V_OR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
 >;
 
 def : GCNPat <
   (xor i16:$src0, i16:$src1),
-  (V_XOR_B32_e64 $src0, $src1)
+  (V_XOR_B32_e64 VSrc_b32:$src0, VSrc_b32:$src1)
 >;
 
 let Predicates = [Has16BitInsts, isGFX7GFX8GFX9] in {

diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
index 799b7cd61204f9c5b7ec2a10d84d4c4572ddf848..361486c1051ce92fe7417291ae917b163bb9cfa8 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
@@ -156,12 +156,11 @@ body: |
     ; WAVE64: S_ENDPGM 0, implicit [[AND]](s16)
     ; WAVE32-LABEL: name: and_s16_vgpr_vgpr_vgpr
     ; WAVE32: liveins: $vgpr0, $vgpr1
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
-    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
-    ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
-    ; WAVE32: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
-    ; WAVE32: S_ENDPGM 0, implicit [[AND]](s16)
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s16) = G_TRUNC %0

diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
index 6e65cda1df93dbf29eb02b28990c4a3dbde214ae..d4df9f9a40316e5d57136f5c67cba55d59ceacf5 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
@@ -156,12 +156,11 @@ body: |
     ; WAVE64: S_ENDPGM 0, implicit [[OR]](s16)
     ; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
     ; WAVE32: liveins: $vgpr0, $vgpr1
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
-    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
-    ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
-    ; WAVE32: [[OR:%[0-9]+]]:vgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
-    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s16)
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s16) = G_TRUNC %0

diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
index b6d88e1a5f6e79f4b2f3cbe95d0b57b7fa3478fd..d6f38009f573085948975026a23c5c27cf0ff9f1 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
@@ -156,12 +156,11 @@ body: |
     ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s16)
     ; WAVE32-LABEL: name: xor_s16_vgpr_vgpr_vgpr
     ; WAVE32: liveins: $vgpr0, $vgpr1
-    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
-    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
-    ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
-    ; WAVE32: [[XOR:%[0-9]+]]:vgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
-    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s16)
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = COPY $vgpr1
     %2:vgpr(s16) = G_TRUNC %0