Fix type of last vector operand of Neon quad-register multiple-lane intrinsics.

The sensible thing would be to have these intrinsics take all quad-register
vector operands, but that's not what ARM did.  They made the last vector
operand always be a double-register type.  Since the lane number
must be a constant, the user can know which half of a quad-register contains
that lane, extract the high or low half of the vector, and adjust the lane
number accordingly.  The only advantage I can see for this is that it works
better when you want to multiply a quad-register value by a lane from a
double-register value, but I wouldn't have expected that to be the common
case.  Oh well -- at this point we just need to follow the spec.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@121397 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td
index a241b68c69d30a300966c5caa9c8c5771ee41b72..ab74d49a192e82c22c93315a0fe2fd22e3f284c0 100644 (file)
--- a/include/clang/Basic/arm_neon.td
+++ b/include/clang/Basic/arm_neon.td
@@ -323,22 +323,22 @@ def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">;
 
 ////////////////////////////////////////////////////////////////////////////////
 // E.3.25 Operations with a scalar value
-def VMLA_LANE    : Inst<"vmla_lane", "ddddi", "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
+def VMLA_LANE    : Inst<"vmla_lane", "dddgi", "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
 def VMLAL_LANE   : Inst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>;
 def VQDMLAL_LANE : Inst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 
-def VMLS_LANE    : Inst<"vmls_lane", "ddddi", "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
+def VMLS_LANE    : Inst<"vmls_lane", "dddgi", "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
 def VMLSL_LANE   : Inst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>;
 def VQDMLSL_LANE : Inst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
 def VMUL_N       : Inst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
-def VMUL_LANE    : Inst<"vmul_lane", "dddi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
+def VMUL_LANE    : Inst<"vmul_lane", "ddgi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
 def VMULL_N      : Inst<"vmull_n", "wda", "siUsUi", OP_MULL_N>;
 def VMULL_LANE   : Inst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
 def VQDMULL_N    : SInst<"vqdmull_n", "wda", "si">;
 def VQDMULL_LANE : Inst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
 def VQDMULH_N    : SInst<"vqdmulh_n", "dda", "siQsQi">;
-def VQDMULH_LANE : Inst<"vqdmulh_lane", "dddi", "siQsQi", OP_QDMULH_LN>;
+def VQDMULH_LANE : Inst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>;
 def VQRDMULH_N   : SInst<"vqrdmulh_n", "dda", "siQsQi">;
-def VQRDMULH_LANE : Inst<"vqrdmulh_lane", "dddi", "siQsQi", OP_QRDMULH_LN>;
+def VQRDMULH_LANE : Inst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>;
 def VMLA_N       : Inst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>;
 def VMLAL_N      : Inst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>;
 def VQDMLAL_N    : SInst<"vqdmlal_n", "wwda", "si">;