[AArch64] auto-generate complete test checks; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361908 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/AArch64/sdag-store-merging-bug.ll b/test/CodeGen/AArch64/sdag-store-merging-bug.ll
index b12dc0933fc08cf8f4e22fae8d1cf9e42bc13e4d..d67988de575278c66520e08f8057338eca769c4d 100644 (file)
--- a/test/CodeGen/AArch64/sdag-store-merging-bug.ll
+++ b/test/CodeGen/AArch64/sdag-store-merging-bug.ll
@@ -1,20 +1,22 @@
-; RUN: llc -o - %s -mtriple aarch64-- -mattr +slow-misaligned-128store -stop-after=instruction-select | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -o - %s -mtriple aarch64-- -mattr +slow-misaligned-128store | FileCheck %s
 ; Checks for a bug where selection dag store merging would construct wrong
 ; indices when extracting values from vectors, resulting in an invalid
 ; lane duplication in this case.
 ; The only way I could trigger stores with mismatching types getting merged was
 ; via the aarch64 slow-misaligned-128store code splitting stores earlier.
 
-; CHECK-LABEL: name: func
-; CHECK: LDRQui
-; CHECK-NOT: INSERT_SUBREG
-; CHECK-NOT: DUP
-; CHECK-NEXT: STRQui
+; aarch64 feature slow-misaligned-128store splits the following store.
+; store merging immediately merges it back together (but used to get the
+; merging wrong), this is the only way I was able to reproduce the bug...
+
 define void @func(<2 x double>* %sptr, <2 x double>* %dptr) {
+; CHECK-LABEL: func:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    str q0, [x1]
+; CHECK-NEXT:    ret
   %load = load <2 x double>, <2 x double>* %sptr, align 8
-  ; aarch64 feature slow-misaligned-128store splits the following store.
-  ; store merging immediately merges it back together (but used to get the
-  ; merging wrong), this is the only way I was able to reproduce the bug...
   store <2 x double> %load, <2 x double>* %dptr, align 4
   ret void
 }