Use store size instead of alloc size when coercing.

Previously, EnterStructPointerForCoercedAccess used Alloc size when determining how to convert. This was problematic, because there were situations were the alloc size was larger than the store size. For example, if the first element of a structure were i24 and the destination type were i32, the old code would generate a GEP and a load i24. The code should compare store sizes to ensure the whole object is loaded. I have attached a test case.

This patch modifies the output of arm64-be-bitfield.c test case, but the new IR seems to be equivalent, and after -O3, the compiler generates identical ARM assembly. (asr x0, x0, #54)

Patch by Thomas Jablin!

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@216722 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/CGCall.cpp b/lib/CodeGen/CGCall.cpp
index 75713419aa11aaa85b3b1a84a6e7267aa7fdeaf2..aa7de709cb5510fe2945116020dfa9430b1a19a0 100644 (file)
--- a/lib/CodeGen/CGCall.cpp
+++ b/lib/CodeGen/CGCall.cpp
@@ -627,11 +627,13 @@ EnterStructPointerForCoercedAccess(llvm::Value *SrcPtr,
   llvm::Type *FirstElt = SrcSTy->getElementType(0);
 
   // If the first elt is at least as large as what we're looking for, or if the
-  // first element is the same size as the whole struct, we can enter it.
+  // first element is the same size as the whole struct, we can enter it. The
+  // comparison must be made on the store size and not the alloca size. Using
+  // the alloca size may overstate the size of the load.
   uint64_t FirstEltSize =
-    CGF.CGM.getDataLayout().getTypeAllocSize(FirstElt);
+    CGF.CGM.getDataLayout().getTypeStoreSize(FirstElt);
   if (FirstEltSize < DstSize &&
-      FirstEltSize < CGF.CGM.getDataLayout().getTypeAllocSize(SrcSTy))
+      FirstEltSize < CGF.CGM.getDataLayout().getTypeStoreSize(SrcSTy))
     return SrcPtr;
 
   // GEP into the first element.

diff --git a/test/CodeGen/24-bit.c b/test/CodeGen/24-bit.c
new file mode 100644 (file)
index 0000000..9dd0157
--- /dev/null
+++ b/test/CodeGen/24-bit.c
@@ -0,0 +1,14 @@
+// RUN:  %clang_cc1 -triple x86_64-linux-gnu -emit-llvm -O0 -o - %s | FileCheck %s
+
+static union ibtt2
+{
+  struct ibtt0 { signed ibt0:10; unsigned short ibt1; } ibt5;
+  struct ibtt1 { signed ibt2:3; signed ibt3:9; signed ibt4:9; } ibt6;
+} ibt15 = {{267, 15266}};
+
+void callee_ibt0f(union ibtt2 ibtp5);
+
+void test(void) {
+// CHECK: = load i32*
+  callee_ibt0f(ibt15);
+}

diff --git a/test/CodeGen/arm64-be-bitfield.c b/test/CodeGen/arm64-be-bitfield.c
index 2fe467bcf1a4155bb0b30693fba6be9e5fbce73a..b8d497c5580def6fcf03ebdf9121058ae351bcd9 100644 (file)
--- a/test/CodeGen/arm64-be-bitfield.c
+++ b/test/CodeGen/arm64-be-bitfield.c
@@ -1,9 +1,15 @@
-// RUN:  %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -emit-llvm -O0 -o - %s | FileCheck %s
+// REQUIRES: aarch64-registered-target
+// RUN:  %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -emit-llvm -O0 -o - %s | FileCheck --check-prefix IR %s
+// RUN:  %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -S -O1 -o - %s | FileCheck --check-prefix ARM %s
 
 struct bt3 { signed b2:10; signed b3:10; } b16;
 
-// The correct right-shift amount is 40 bits for big endian.
+// Get the high 32-bits and then shift appropriately for big-endian.
 signed callee_b0f(struct bt3 bp11) {
-// CHECK: = lshr i64 %{{.*}}, 40
+// IR: callee_b0f(i64 [[ARG:%.*]])
+// IR: store i64 [[ARG]], i64* [[PTR:%.*]]
+// IR: [[BITCAST:%.*]] = bitcast i64* [[PTR]] to i8*
+// IR: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* [[BITCAST]], i64 4
+// ARM: asr x0, x0, #54
   return bp11.b2;
 }