]> granicus.if.org Git - llvm/commitdiff
bpf: set missing types in insn tablegen file
authorYonghong Song <yhs@fb.com>
Fri, 16 Jun 2017 15:30:55 +0000 (15:30 +0000)
committerYonghong Song <yhs@fb.com>
Fri, 16 Jun 2017 15:30:55 +0000 (15:30 +0000)
o This is discovered during my study of 32-bit subregister
  support.
o This is no impact on current functionality since we
  only support 64-bit registers.
o Searching the web, looks like the issue has been discovered
  before, so fix it now.

Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305559 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/BPF/BPFInstrInfo.td

index c6c0ff587c6b87682c6b8000f4769b0008198dcf..5ad77726820843bd6ec5e8d6114733820c407d6e 100644 (file)
@@ -51,7 +51,7 @@ def u64imm   : Operand<i64> {
   let PrintMethod = "printImm64Operand";
 }
 
-def i64immSExt32 : PatLeaf<(imm),
+def i64immSExt32 : PatLeaf<(i64 imm),
                 [{return isInt<32>(N->getSExtValue()); }]>;
 
 // Addressing modes.
@@ -67,17 +67,17 @@ def MEMri : Operand<i64> {
 }
 
 // Conditional code predicates - used for pattern matching for jump instructions
-def BPF_CC_EQ  : PatLeaf<(imm),
+def BPF_CC_EQ  : PatLeaf<(i64 imm),
                          [{return (N->getZExtValue() == ISD::SETEQ);}]>;
-def BPF_CC_NE  : PatLeaf<(imm),
+def BPF_CC_NE  : PatLeaf<(i64 imm),
                          [{return (N->getZExtValue() == ISD::SETNE);}]>;
-def BPF_CC_GE  : PatLeaf<(imm),
+def BPF_CC_GE  : PatLeaf<(i64 imm),
                          [{return (N->getZExtValue() == ISD::SETGE);}]>;
-def BPF_CC_GT  : PatLeaf<(imm),
+def BPF_CC_GT  : PatLeaf<(i64 imm),
                          [{return (N->getZExtValue() == ISD::SETGT);}]>;
-def BPF_CC_GTU : PatLeaf<(imm),
+def BPF_CC_GTU : PatLeaf<(i64 imm),
                          [{return (N->getZExtValue() == ISD::SETUGT);}]>;
-def BPF_CC_GEU : PatLeaf<(imm),
+def BPF_CC_GEU : PatLeaf<(i64 imm),
                          [{return (N->getZExtValue() == ISD::SETUGE);}]>;
 
 // jump instructions