[PowerPC] Automatically generate various tests. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369700 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/PowerPC/testComparesi32gtu.ll b/test/CodeGen/PowerPC/testComparesi32gtu.ll
index 62d66c5747b912e48f681a5a65dd219f9aced1b5..2f2a32a731319db0a00f7e28b5f2a63f45579f60 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesi32gtu.ll
+++ b/test/CodeGen/PowerPC/testComparesi32gtu.ll
@@ -1,25 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 %struct.tree_common = type { i8, [3 x i8] }
 declare signext i32 @fn2(...) local_unnamed_addr #1
 
 ; Function Attrs: nounwind
 define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
-; CHECK-LABEL: testCompare1:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         lbz r3, 0(r3)
-; CHECK-DAG:     clrlwi r3, r3, 31
-; CHECK-DAG:     clrldi r3, r3, 32
-; CHECK:         lbz  r4, 0(r4)
-; CHECK-DAG:     clrlwi r4, r4, 31
-; CHECK-DAG:     clrldi r4, r4, 32
-; CHECK:         sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; BE-LABEL: testCompare1:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    mflr r0
+; BE-NEXT:    std r0, 16(r1)
+; BE-NEXT:    stdu r1, -112(r1)
+; BE-NEXT:    .cfi_def_cfa_offset 112
+; BE-NEXT:    .cfi_offset lr, 16
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    lbz r3, 0(r3)
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    clrlwi r3, r3, 31
+; BE-NEXT:    clrldi r3, r3, 32
+; BE-NEXT:    lbz r4, 0(r4)
+; BE-NEXT:    clrlwi r4, r4, 31
+; BE-NEXT:    clrldi r4, r4, 32
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    bl fn2
+; BE-NEXT:    nop
+; BE-NEXT:    addi r1, r1, 112
+; BE-NEXT:    ld r0, 16(r1)
+; BE-NEXT:    mtlr r0
+; BE-NEXT:    blr
+;
+; LE-LABEL: testCompare1:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    mflr r0
+; LE-NEXT:    std r0, 16(r1)
+; LE-NEXT:    stdu r1, -32(r1)
+; LE-NEXT:    .cfi_def_cfa_offset 32
+; LE-NEXT:    .cfi_offset lr, 16
+; LE-NEXT:    addis r4, r2, .LC0@toc@ha
+; LE-NEXT:    lbz r3, 0(r3)
+; LE-NEXT:    ld r4, .LC0@toc@l(r4)
+; LE-NEXT:    clrlwi r3, r3, 31
+; LE-NEXT:    clrldi r3, r3, 32
+; LE-NEXT:    lbz r4, 0(r4)
+; LE-NEXT:    clrlwi r4, r4, 31
+; LE-NEXT:    clrldi r4, r4, 32
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    bl fn2
+; LE-NEXT:    nop
+; LE-NEXT:    addi r1, r1, 32
+; LE-NEXT:    ld r0, 16(r1)
+; LE-NEXT:    mtlr r0
+; LE-NEXT:    blr
 entry:
   %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
   %bf.clear = and i8 %bf.load, 1
@@ -36,11 +76,11 @@ entry:
 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
-; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
-; CHECK-DAG:     clrldi r3, r3, 32
-; CHECK-DAG:     clrldi r4, r4, 32
-; CHECK:         sub r3, r4, r3
+; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
+; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:

diff --git a/test/CodeGen/PowerPC/testComparesi32ltu.ll b/test/CodeGen/PowerPC/testComparesi32ltu.ll
index 2b9d0ef1faaf4077904dbe3fdf289d37a432afee..5c228853c5aaa72332439fe447c08cc49111b5eb 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesi32ltu.ll
+++ b/test/CodeGen/PowerPC/testComparesi32ltu.ll
@@ -1,25 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 %struct.tree_common = type { i8, [3 x i8] }
 declare signext i32 @fn2(...) local_unnamed_addr #1
 
 ; Function Attrs: nounwind
 define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
-; CHECK-LABEL: testCompare1:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         lbz r3, 0(r3)
-; CHECK-DAG:     clrlwi r3, r3, 31
-; CHECK-DAG:     clrldi r3, r3, 32
-; CHECK:         lbz  r4, 0(r4)
-; CHECK-DAG:     clrlwi r4, r4, 31
-; CHECK-DAG:     clrldi r4, r4, 32
-; CHECK:         sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; BE-LABEL: testCompare1:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    mflr r0
+; BE-NEXT:    std r0, 16(r1)
+; BE-NEXT:    stdu r1, -112(r1)
+; BE-NEXT:    .cfi_def_cfa_offset 112
+; BE-NEXT:    .cfi_offset lr, 16
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    lbz r3, 0(r3)
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    clrlwi r3, r3, 31
+; BE-NEXT:    clrldi r3, r3, 32
+; BE-NEXT:    lbz r4, 0(r4)
+; BE-NEXT:    clrlwi r4, r4, 31
+; BE-NEXT:    clrldi r4, r4, 32
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    bl fn2
+; BE-NEXT:    nop
+; BE-NEXT:    addi r1, r1, 112
+; BE-NEXT:    ld r0, 16(r1)
+; BE-NEXT:    mtlr r0
+; BE-NEXT:    blr
+;
+; LE-LABEL: testCompare1:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    mflr r0
+; LE-NEXT:    std r0, 16(r1)
+; LE-NEXT:    stdu r1, -32(r1)
+; LE-NEXT:    .cfi_def_cfa_offset 32
+; LE-NEXT:    .cfi_offset lr, 16
+; LE-NEXT:    addis r4, r2, .LC0@toc@ha
+; LE-NEXT:    lbz r3, 0(r3)
+; LE-NEXT:    ld r4, .LC0@toc@l(r4)
+; LE-NEXT:    clrlwi r3, r3, 31
+; LE-NEXT:    clrldi r3, r3, 32
+; LE-NEXT:    lbz r4, 0(r4)
+; LE-NEXT:    clrlwi r4, r4, 31
+; LE-NEXT:    clrldi r4, r4, 32
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    bl fn2
+; LE-NEXT:    nop
+; LE-NEXT:    addi r1, r1, 32
+; LE-NEXT:    ld r0, 16(r1)
+; LE-NEXT:    mtlr r0
+; LE-NEXT:    blr
 entry:
   %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
   %bf.clear = and i8 %bf.load, 1
@@ -36,11 +76,11 @@ entry:
 define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: testCompare2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-DAG:     rlwinm r3, r3, 0, 31, 31
-; CHECK-DAG:     rlwinm r4, r4, 0, 31, 31
-; CHECK-DAG:     clrldi r3, r3, 32
-; CHECK-DAG:     clrldi r4, r4, 32
-; CHECK:         sub r3, r3, r4
+; CHECK-NEXT:    rlwinm r3, r3, 0, 31, 31
+; CHECK-NEXT:    rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    clrldi r4, r4, 32
+; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:

diff --git a/test/CodeGen/PowerPC/testComparesigeuc.ll b/test/CodeGen/PowerPC/testComparesigeuc.ll
index c36b6a5e2e0327bad3707c49e7f19776fd6f08db..5047f0fbee1592fabec7aba751dfc4fd089925ee 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigeuc.ll
+++ b/test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -1,77 +1,116 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igeuc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: test_igeuc:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igeuc_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr  
-  
+
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igeuc_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: @test_igeuc_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr  
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igeuc_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv2 = sext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: @test_igeuc_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr  
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_igeuc_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeuc_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
 ; CHECK_LABEL: test_igeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_igeuc_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeuc_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -82,31 +121,51 @@ entry:
 ; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
 ; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1
 ; CHECK-TBD: stb  [[REG3]]
-; CHECK-TBD: blr    
+; CHECK-TBD: blr
 }
 
 ; Function Attrs : norecurse nounwind
 define void @test_igeuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_igeuc_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stb r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeuc_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    stb r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK-LABEL: @test_igeuc_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stb [[REG1]]
-; CHECK: blr    
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_igeuc_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stb r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeuc_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    stb r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK-LABEL: @test_igeuc_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stb [[REG1]]
-; CHECK: blr
 }

diff --git a/test/CodeGen/PowerPC/testComparesigeui.ll b/test/CodeGen/PowerPC/testComparesigeui.ll
index bec1e21c586f89f6e0866741ebefcbbc0b68c8f4..48a0677a44a8ce9769452c2721beb893626bb4be 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigeui.ll
+++ b/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igeui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK-LABEL: test_igeui:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igeui_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr    
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igeui_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %sub = zext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeui_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igeui_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeui_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_igeui_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeui_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
 ; CHECK_LABEL: test_igeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_igeui_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeui_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_igeui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw  [[REG3]]
-; CHECK: blr    
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_igeui_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeui_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    stw r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %conv1 = zext i1 %cmp to i32
   store i32 %conv1, i32* @glob
   ret void
-; CHECK-LABEL: @test_igeui_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stw [[REG1]]
-; CHECK: blr  
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_igeui_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeui_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    stw r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
-  %cmp = icmp uge i32 %a, 0 
+  %cmp = icmp uge i32 %a, 0
   %conv1 = sext i1 %cmp to i32
   store i32 %conv1, i32* @glob
   ret void
-; CHECK-LABEL: @test_igeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stw [[REG1]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesigeull.ll b/test/CodeGen/PowerPC/testComparesigeull.ll
index 103eeb1c7059361de2bc9a9bba2622bd349b058a..53f0e2ac47d1bb48399564743afad2084d92c558 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigeull.ll
+++ b/test/CodeGen/PowerPC/testComparesigeull.ll
@@ -1,111 +1,163 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igeull:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK-LABEL: test_igeull:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igeull_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not r3, [[REG2]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeull_z(i64 %a) {
+; CHECK-LABEL: test_igeull_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %sub = zext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeull_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeull_sext_z(i64 %a) {
+; CHECK-LABEL: test_igeull_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeull_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_igeull_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    ld r3, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r4, r4, r4
+; BE-NEXT:    addi r4, r4, 1
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeull_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r4, r4
+; LE-NEXT:    addi r3, r3, 1
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: test_igeull_store:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_igeull_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    ld r3, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r4, r4, r4
+; BE-NEXT:    not r4, r4
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeull_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r4, r4
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_igeull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeull_z_store(i64 %a) {
+; BE-LABEL: test_igeull_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeull_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    std r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_igeull_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: std [[REG1]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeull_sext_z_store(i64 %a) {
+; BE-LABEL: test_igeull_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeull_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    std r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_igeull_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: std [[REG1]]
-; CHECK: blr
 }

diff --git a/test/CodeGen/PowerPC/testComparesigeus.ll b/test/CodeGen/PowerPC/testComparesigeus.ll
index 33266e04a11365113ee5c0a97de07b3c5a34ee50..ede0e42bcbf3897c0708a62e572dc86a5bb11af9 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigeus.ll
+++ b/test/CodeGen/PowerPC/testComparesigeus.ll
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igeus:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: test_igeus:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igeus_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_igeus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igeus_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: @test_igeus_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igeus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igeus_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: @test_igeus_sext_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_igeus_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeus_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
 ; CHECK_LABEL: test_igeus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_igeus_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeus_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: @test_igeus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_igeus_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    sth r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeus_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    sth r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: @test_igeus_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: sth [[REG1]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_igeus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_igeus_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    sth r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_igeus_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    sth r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: @test_igeus_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: sth [[REG1]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesigtsc.ll b/test/CodeGen/PowerPC/testComparesigtsc.ll
index c669d694c435a50f796838c8d549bff6f3d23a1f..9ae7e5d0a90969f30f11842a2b8ea4f87a4f08ce 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigtsc.ll
+++ b/test/CodeGen/PowerPC/testComparesigtsc.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
 define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, %b
@@ -24,8 +25,8 @@ entry:
 define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, %b
@@ -50,9 +51,10 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_igtsc_sext_z:
-; CHECK: neg [[REG2:r[0-9]+]], r3
-; CHECK-NEXT: sradi r3, [[REG2]], 63
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, 0
   %sub = sext i1 %cmp to i32
@@ -63,8 +65,12 @@ entry:
 define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -76,8 +82,12 @@ entry:
 define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_igtsc_sext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -106,8 +116,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsc_sext_z_store(i8 signext %a) {
 ; CHECK-LABEL: test_igtsc_sext_z_store:
-; CHECK:       neg [[REG2:r[0-9]+]], r3
-; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, 0
   %conv2 = sext i1 %cmp to i8

diff --git a/test/CodeGen/PowerPC/testComparesigtsi.ll b/test/CodeGen/PowerPC/testComparesigtsi.ll
index 9b5f1f43c7e7b7256235874b15214553f2f79541..ecdc2f7b4746ddaec8eec5fcb99b80891198009b 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigtsi.ll
+++ b/test/CodeGen/PowerPC/testComparesigtsi.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
 define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, %b
@@ -24,8 +25,8 @@ entry:
 define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, %b
@@ -50,9 +51,10 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsi_sext_z(i32 signext %a) {
 ; CHECK-LABEL: test_igtsi_sext_z:
-; CHECK:  neg [[REG2:r[0-9]+]], r3
-; CHECK-NEXT: sradi r3, [[REG2]], 63
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
   %sub = sext i1 %cmp to i32
@@ -63,8 +65,12 @@ entry:
 define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -76,8 +82,12 @@ entry:
 define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_igtsi_sext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -106,8 +116,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsi_sext_z_store(i32 signext %a) {
 ; CHECK-LABEL: test_igtsi_sext_z_store:
-; CHECK: neg [[REG:r[0-9]+]], r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stw r3, 0(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
   %sub = sext i1 %cmp to i32

diff --git a/test/CodeGen/PowerPC/testComparesigtsll.ll b/test/CodeGen/PowerPC/testComparesigtsll.ll
index c2198d10bc50ec3713d032dd88e5759db09d0fa1..d1f89d9aef1aaf4a7016c7934a7f3a84025c3f78 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigtsll.ll
+++ b/test/CodeGen/PowerPC/testComparesigtsll.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,11 +12,11 @@
 define signext i32 @test_igtsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -27,12 +28,12 @@ entry:
 define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -58,9 +59,11 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_igtsll_sext_z:
-; CHECK:    addi [[REG1:r[0-9]+]], r3, -1
-; CHECK-NEXT:    nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK-NEXT:    sradi r3, [[REG2]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    nor r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   %sub = sext i1 %cmp to i32
@@ -71,12 +74,16 @@ entry:
 define void @test_igtsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT:     neg
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -88,12 +95,17 @@ entry:
 define void @test_igtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_igtsll_sext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK:         neg {{r[0-9]+}}, [[REG5]]
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -123,9 +135,14 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtsll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_igtsll_sext_z_store:
-; CHECK:    addi [[REG1:r[0-9]+]], r3, -1
-; CHECK:    nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK:    sradi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r5, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   %conv1 = sext i1 %cmp to i64

diff --git a/test/CodeGen/PowerPC/testComparesigtss.ll b/test/CodeGen/PowerPC/testComparesigtss.ll
index 93e6ccd53bd265c22b2d0b399be6aebfff57e253..f6fa43a53049834256afeafcc89ceca758152066 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigtss.ll
+++ b/test/CodeGen/PowerPC/testComparesigtss.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
 define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, %b
@@ -24,8 +25,8 @@ entry:
 define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, %b
@@ -51,8 +52,8 @@ entry:
 define signext i32 @test_igtss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_igtss_sext_z:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:    neg [[REG2:r[0-9]+]], r3
-; CHECK-NEXT:    sradi r3, [[REG2]], 63
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, 0
@@ -64,8 +65,12 @@ entry:
 define void @test_igtss_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG1:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -77,8 +82,12 @@ entry:
 define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_igtss_sext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -107,8 +116,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtss_sext_z_store(i16 signext %a) {
 ; CHECK-LABEL: test_igtss_sext_z_store:
-; CHECK:       neg [[REG2:r[0-9]+]], r3
-; CHECK:       sradi {{r[0-9]+}}, [[REG2]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, 0
   %conv2 = sext i1 %cmp to i16

diff --git a/test/CodeGen/PowerPC/testComparesigtuc.ll b/test/CodeGen/PowerPC/testComparesigtuc.ll
index 2886130dfba4404a25c27141805f5f2afe06fb76..51a29746c0f5d5aafca6e98d26dd13e803dd3c12 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigtuc.ll
+++ b/test/CodeGen/PowerPC/testComparesigtuc.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igtuc:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -22,8 +24,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igtuc_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -34,7 +37,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtuc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_igtuc_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -47,7 +51,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtuc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_igtuc_sext_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -61,8 +66,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igtuc_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -73,8 +83,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_igtuc_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -85,10 +100,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtuc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_igtuc_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    stb r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 0
@@ -100,11 +118,14 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtuc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_igtuc_sext_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    neg r3, r3
-; CHECK:    stb r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 0

diff --git a/test/CodeGen/PowerPC/testComparesigtui.ll b/test/CodeGen/PowerPC/testComparesigtui.ll
index a81a1a64f617ed1a4e7edf278806695556c4ffeb..db80bef1569bab58970c2847254d21767534e8b9 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigtui.ll
+++ b/test/CodeGen/PowerPC/testComparesigtui.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igtui:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
@@ -22,8 +24,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igtui_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
@@ -34,7 +37,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtui_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_igtui_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -47,7 +51,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtui_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_igtui_sext_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -61,8 +66,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igtui_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -73,8 +83,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_igtui_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -85,10 +100,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtui_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_igtui_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    stw r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, 0
@@ -100,11 +118,14 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtui_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_igtui_sext_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    neg r3, r3
-; CHECK:    stw r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, 0

diff --git a/test/CodeGen/PowerPC/testComparesigtus.ll b/test/CodeGen/PowerPC/testComparesigtus.ll
index 7beca852c166d9ca405a2f061067ddbccfaac99f..ffcd468ab0d426ca9ff9485a6b29da2d4f863891 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesigtus.ll
+++ b/test/CodeGen/PowerPC/testComparesigtus.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igtus:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -22,8 +24,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igtus_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -34,7 +37,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtus_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_igtus_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -47,7 +51,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_igtus_sext_z(i16 zeroext %a) {
 ; CHECK-LABEL: test_igtus_sext_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -61,9 +66,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igtus_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
-; CHECK:         blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -74,9 +83,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_igtus_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
-; CHECK:         blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -87,10 +100,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtus_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_igtus_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    sth r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, 0
@@ -102,11 +118,14 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_igtus_sext_z_store(i16 zeroext %a) {
 ; CHECK-LABEL: test_igtus_sext_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    neg r3, r3
-; CHECK:    sth r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i16 %a, 0

diff --git a/test/CodeGen/PowerPC/testComparesileuc.ll b/test/CodeGen/PowerPC/testComparesileuc.ll
index 3084b7ee9ed29d201ea332f571c05eda2b047c4d..9976dada86b3d2b3bd8dd35515a1a2fe6c6166db 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesileuc.ll
+++ b/test/CodeGen/PowerPC/testComparesileuc.ll
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ileuc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: test_ileuc:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ileuc_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ileuc_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv1 = zext i1 %cmp to i32
   ret i32 %conv1
-; CHECK-LABEL: test_ileuc_z:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi r3, [[REG1]], 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ileuc_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileuc_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_ileuc_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileuc_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK-LABEL: test_ileuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_ileuc_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileuc_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK-LABEL: @test_ileuc_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stb  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_ileuc_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileuc_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    stb r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = zext i1 %cmp to i8
   store i8 %conv2, i8* @glob
   ret void
-; CHECK-LABEL: test_ileuc_z_store:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_ileuc_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileuc_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    stb r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp eq i8 %a, 0
   %conv2 = sext i1 %cmp to i8
   store i8 %conv2, i8* @glob
   ret void
-; CHECK-LABEL: @test_ileuc_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stb [[REG3]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesileui.ll b/test/CodeGen/PowerPC/testComparesileui.ll
index addaa9b991ed0c1d3586949814f6924a03e678f6..dc69277111c9cdd88818fc4165f0fe9dadc96d97 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesileui.ll
+++ b/test/CodeGen/PowerPC/testComparesileui.ll
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ileui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = zext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: test_ileui:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ileui_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ileui_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = zext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: test_ileui_z:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi r3, [[REG1]], 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ileui_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileui_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_ileui_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileui_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = zext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: test_ileui_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_ileui_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileui_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_ileui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_ileui_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileui_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    stw r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = zext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: test_ileui_z_store:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_ileui_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileui_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    stw r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %a, 0
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_ileui_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stw [[REG3]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesileull.ll b/test/CodeGen/PowerPC/testComparesileull.ll
index afcf0ce4bbdb0d593f9af536f3af742bde701c85..4b18754d7966863b2456a03bcbeff7a2395faf25 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesileull.ll
+++ b/test/CodeGen/PowerPC/testComparesileull.ll
@@ -1,115 +1,170 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ileull:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK-LABEL: test_ileull:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ileull_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not r3, [[REG2]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileull_z(i64 %a) {
+; CHECK-LABEL: test_ileull_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK-LABEL: test_ileull_z
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileull_sext_z(i64 %a) {
+; CHECK-LABEL: test_ileull_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileull_sext_z
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe r3, [[REG1]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_ileull_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r3, r3, r3
+; BE-NEXT:    addi r3, r3, 1
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileull_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r3, r3
+; LE-NEXT:    addi r3, r3, 1
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: test_ileull_store:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_ileull_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r3, r3, r3
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileull_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r3, r3
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_ileull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileull_z_store(i64 %a) {
+; BE-LABEL: test_ileull_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzd r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    rldicl r3, r3, 58, 63
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileull_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzd r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 58, 63
+; LE-NEXT:    std r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: test_ileull_z_store:
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileull_sext_z_store(i64 %a) {
+; BE-LABEL: test_ileull_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    addic r3, r3, -1
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    subfe r3, r3, r3
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileull_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addic r3, r3, -1
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_ileull_sext_z_store
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: std [[REG2]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesileus.ll b/test/CodeGen/PowerPC/testComparesileus.ll
index 122d46f24c60b3275b18fd4cdc4e2710b3b8afa9..0cb21e0b28e10ac13077dbe278d0eaece70fd275 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesileus.ll
+++ b/test/CodeGen/PowerPC/testComparesileus.ll
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ileus:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv2 = zext i1 %cmp to i32
   ret i32 %conv2
-; CHECK-LABEL: test_ileus:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ileus_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ileus_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv1 = zext i1 %cmp to i32
   ret i32 %conv1
-; CHECK-LABEL: test_ileus_z:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi r3, [[REG1]], 5
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_ileus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ileus_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK-LABEL: @test_ileus_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_ileus_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileus_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: test_ileus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_ileus_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileus_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: @test_ileus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_ileus_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileus_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    sth r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = zext i1 %cmp to i16
   store i16 %conv2, i16* @glob
   ret void
-; CHECK-LABEL: test_ileus_z_store:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_ileus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_ileus_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_ileus_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    sth r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = sext i1 %cmp to i16
   store i16 %conv2, i16* @glob
   ret void
-; CHECK-LABEL: @test_ileus_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: sth [[REG3]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesiltsc.ll b/test/CodeGen/PowerPC/testComparesiltsc.ll
index 08a023302bddf2ebc267e8921233b0bdc41ac100..7702598c5ffb18ff7b0225281f15aaa62d64bf73 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesiltsc.ll
+++ b/test/CodeGen/PowerPC/testComparesiltsc.ll
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
@@ -12,8 +14,8 @@
 define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
@@ -25,8 +27,8 @@ entry:
 define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: test_iltsc_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
@@ -37,8 +39,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltsc_sext_z(i8 signext %a) {
 ; CHECK-LABEL: test_iltsc_sext_z:
-; CHECK:       srawi r3, r3, 31
-; CHECK-NEXT:  blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, 0
   %sub = sext i1 %cmp to i32
@@ -47,10 +50,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_iltsc_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltsc_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stb r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsc_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -60,10 +75,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_iltsc_sext_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltsc_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    stb r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsc_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -73,8 +100,20 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsc_sext_z_store(i8 signext %a) {
-; CHECK-LABEL: test_iltsc_sext_z_store:
-; CHECK: srwi {{r[0-9]+}}, r3, 7
+; BE-LABEL: test_iltsc_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    srwi r3, r3, 7
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsc_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 7
+; LE-NEXT:    stb r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, 0
   %conv2 = sext i1 %cmp to i8

diff --git a/test/CodeGen/PowerPC/testComparesiltsi.ll b/test/CodeGen/PowerPC/testComparesiltsi.ll
index 39f37387f534f6e6e0f0726fe6d42192088cfed4..a97b734a8e41fdd0b695fc9e7c2ea1081d53ff60 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesiltsi.ll
+++ b/test/CodeGen/PowerPC/testComparesiltsi.ll
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i32 0, align 4
 
@@ -12,8 +14,8 @@
 define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
@@ -25,8 +27,8 @@ entry:
 define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: test_iltsi_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
@@ -48,10 +50,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
-; CHECK-LABEL: test_iltsi_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltsi_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stw r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsi_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -61,10 +75,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
-; CHECK-LABEL: test_iltsi_sext_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltsi_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    stw r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsi_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -74,9 +100,20 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsi_sext_z_store(i32 signext %a) {
-; CHECK-LABEL: test_iltsi_sext_z_store:
-; CHECK:    srawi {{r[0-9]+}}, r3, 31
-; CHECK:    blr
+; BE-LABEL: test_iltsi_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    srawi r3, r3, 31
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsi_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srawi r3, r3, 31
+; LE-NEXT:    stw r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, 0
   %sub = sext i1 %cmp to i32

diff --git a/test/CodeGen/PowerPC/testComparesiltsll.ll b/test/CodeGen/PowerPC/testComparesiltsll.ll
index 4152b8556df00e0f0bbf817b7a0153a4f99a07d4..0341c158fe2b2b713f382d872badb66bf241372c 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesiltsll.ll
+++ b/test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i64 0, align 8
 
@@ -12,11 +14,11 @@
 define signext i32 @test_iltsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -28,12 +30,12 @@ entry:
 define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_iltsll_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -55,14 +57,29 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsll_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_iltsll_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_iltsll_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    sradi r6, r3, 63
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    adde r3, r3, r6
+; BE-NEXT:    xori r3, r3, 1
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsll_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sradi r6, r3, 63
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    adde r3, r3, r6
+; LE-NEXT:    xori r3, r3, 1
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT:     neg {{r[0-9]+}}, [[REG5]]
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -72,14 +89,31 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsll_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_iltsll_sext_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_iltsll_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    sradi r6, r3, 63
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    adde r3, r3, r6
+; BE-NEXT:    xori r3, r3, 1
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsll_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sradi r6, r3, 63
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    adde r3, r3, r6
+; LE-NEXT:    xori r3, r3, 1
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK:         neg {{r[0-9]+}}, [[REG5]]
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -89,8 +123,20 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltsll_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_iltsll_sext_z_store:
-; CHECK:    sradi r3, r3, 63
+; BE-LABEL: test_iltsll_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltsll_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    std r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 0
   %conv2 = sext i1 %cmp to i64

diff --git a/test/CodeGen/PowerPC/testComparesiltss.ll b/test/CodeGen/PowerPC/testComparesiltss.ll
index db5a60dfb66b4c9b56fe11dbdcaacc72e64bca8c..195a5cf58a81949858953edbf83075a4c136a6c6 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesiltss.ll
+++ b/test/CodeGen/PowerPC/testComparesiltss.ll
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
@@ -12,8 +14,8 @@
 define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
@@ -25,8 +27,8 @@ entry:
 define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: test_iltss_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
@@ -37,8 +39,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltss_sext_z(i16 signext %a) {
 ; CHECK-LABEL: test_iltss_sext_z:
-; CHECK:       srawi r3, r3, 31
-; CHECK-NEXT:  blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    srawi r3, r3, 31
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, 0
   %sub = sext i1 %cmp to i32
@@ -47,10 +50,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltss_store(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: test_iltss_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltss_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    sth r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltss_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -60,10 +75,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: test_iltss_sext_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltss_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    sth r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltss_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
   %conv3 = sext i1 %cmp to i16
@@ -73,8 +100,20 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltss_sext_z_store(i16 signext %a) {
-; CHECK-LABEL: test_iltss_sext_z_store:
-; CHECK:       srwi {{r[0-9]+}}, r3, 15
+; BE-LABEL: test_iltss_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    srwi r3, r3, 15
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltss_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 15
+; LE-NEXT:    sth r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, 0
   %sub = sext i1 %cmp to i16

diff --git a/test/CodeGen/PowerPC/testComparesiltuc.ll b/test/CodeGen/PowerPC/testComparesiltuc.ll
index 19db29a50c99a54a937c5e32a1bb5dcb92a4c75f..64b4fa948a17a8ce7b91ef14cfc08ed5cde940bf 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesiltuc.ll
+++ b/test/CodeGen/PowerPC/testComparesiltuc.ll
@@ -1,17 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iltuc:
-; CHECK:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -22,8 +26,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_iltuc_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -33,9 +38,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_iltuc_store:
-; CHECK:         sub [[REG:r[2-9]+]], r3, r4
-; CHECK:    rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltuc_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stb r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltuc_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -45,9 +63,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_iltuc_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltuc_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    stb r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltuc_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = sext i1 %cmp to i8

diff --git a/test/CodeGen/PowerPC/testComparesiltui.ll b/test/CodeGen/PowerPC/testComparesiltui.ll
index dd9a202cbc998800e614d0dca87a680acd64ad32..005f3b835292940d31eff538e7e2b1f17df919f2 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesiltui.ll
+++ b/test/CodeGen/PowerPC/testComparesiltui.ll
@@ -1,17 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iltui:
-; CHECK:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -22,8 +26,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_iltui_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -33,9 +38,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
-; CHECK-LABEL: test_iltui_store:
-; CHECK:         sub [[REG:r[2-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltui_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stw r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltui_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -45,9 +63,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
-; CHECK-LABEL: test_iltui_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltui_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    stw r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltui_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
   %sub = sext i1 %cmp to i32

diff --git a/test/CodeGen/PowerPC/testComparesiltus.ll b/test/CodeGen/PowerPC/testComparesiltus.ll
index 1174572505983210316b4110f083671ed211771c..20cb9e141a288879885f6277a12fdd0268c4aa2e 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesiltus.ll
+++ b/test/CodeGen/PowerPC/testComparesiltus.ll
@@ -1,17 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iltus:
-; CHECK:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
@@ -22,8 +26,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_iltus_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
@@ -33,9 +38,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_iltus_store:
-; CHECK:         sub [[REG:r[2-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltus_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    sth r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltus_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -45,9 +63,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_iltus_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltus_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    sth r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_iltus_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = sext i1 %cmp to i16

diff --git a/test/CodeGen/PowerPC/testComparesllgeuc.ll b/test/CodeGen/PowerPC/testComparesllgeuc.ll
index f1f50dd5173f7dd523305a74e34fb9d5a47007c1..4c01f87952bf825d8303c84403799097ee438840 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgeuc.ll
+++ b/test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgeuc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: test_llgeuc:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgeuc_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: @test_llgeuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgeuc_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeuc_z
-; CHECK: li r3, 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgeuc_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeuc_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llgeuc_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeuc_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
 ; CHECK_LABEL: test_llgeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llgeuc_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeuc_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK-LABEL: @test_llgeuc_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stb  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llgeuc_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stb r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeuc_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    stb r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv1 = zext i1 %cmp to i8
   store i8 %conv1, i8* @glob
   ret void
-; CHECK-LABEL: @test_llgeuc_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stb [[REG1]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llgeuc_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stb r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeuc_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    stb r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, 0
   %conv1 = sext i1 %cmp to i8
   store i8 %conv1, i8* @glob
   ret void
-; CHECK-LABEL: @test_llgeuc_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stb [[REG1]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllgeui.ll b/test/CodeGen/PowerPC/testComparesllgeui.ll
index 116cc946467ecf2696782e57932031c437e99454..5fc0323d8041f82f52bd59609c553f2e50d878c8 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgeui.ll
+++ b/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgeui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: test_llgeui:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgeui_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr    
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgeui_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeui_z
-; CHECK: li r3, 1
-; CHECK: blr    
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgeui_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeui_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr    
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llgeui_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeui_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
 ; CHECK_LABEL: test_igeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llgeui_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeui_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_llgeui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw  [[REG3]]
-; CHECK: blr  
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llgeui_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeui_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    stw r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %sub = zext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_llgeui_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stw [[REG1]]
-; CHECK: blr  
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llgeui_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeui_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    stw r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, 0
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_llgeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stw [[REG1]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllgeull.ll b/test/CodeGen/PowerPC/testComparesllgeull.ll
index be1db4f754018194d987663caa13e10e1b9609fd..32849572ebb10985b52478c2e0342785b95ffe47 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgeull.ll
+++ b/test/CodeGen/PowerPC/testComparesllgeull.ll
@@ -1,110 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgeull:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: test_llgeull:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgeull_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    subfe r3, r4, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeull_z(i64 %a) {
+; CHECK-LABEL: test_llgeull_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeull_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeull_sext_z(i64 %a) {
+; CHECK-LABEL: test_llgeull_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeull_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llgeull_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    ld r3, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r4, r4, r4
+; BE-NEXT:    addi r4, r4, 1
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeull_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r4, r4
+; LE-NEXT:    addi r3, r3, 1
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: test_llgeull_store:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llgeull_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    ld r3, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r4, r4, r4
+; BE-NEXT:    not r4, r4
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeull_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r4, r4
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, %b
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_llgeull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeull_z_store(i64 %a) {
+; BE-LABEL: test_llgeull_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeull_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    std r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i64 %a, 0
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_llgeull_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: std [[REG1]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeull_sext_z_store(i64 %a) {
+; BE-LABEL: test_llgeull_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeull_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    std r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   store i64 -1, i64* @glob
   ret void
-; CHECK-LABEL: @test_llgeull_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: std [[REG1]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllgeus.ll b/test/CodeGen/PowerPC/testComparesllgeus.ll
index 67d6d190602792bacd51431fd7b68d37a0557b85..552bdd46a16140b8d17329cf1ca7d0709056dbf9 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgeus.ll
+++ b/test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgeus:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: test_llgeus:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgeus_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: @test_llgeus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgeus_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeus_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgeus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgeus_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llgeus_sext_z
-; CHECK: li r3, -1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llgeus_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeus_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
 ; CHECK_LABEL: test_llgeus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llgeus_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeus_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: @test_llgeus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth  [[REG3]]
-; CHECK: blr    
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llgeus_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, 1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    sth r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeus_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, 1
+; LE-NEXT:    sth r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv1 = zext i1 %cmp to i16
   store i16 %conv1, i16* @glob
   ret void
-; CHECK-LABEL: @test_llgeus_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: sth [[REG1]]
-; CHECK: blr  
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llgeus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llgeus_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r3, r2, .LC0@toc@ha
+; BE-NEXT:    li r4, -1
+; BE-NEXT:    ld r3, .LC0@toc@l(r3)
+; BE-NEXT:    sth r4, 0(r3)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llgeus_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r3, r2, glob@toc@ha
+; LE-NEXT:    li r4, -1
+; LE-NEXT:    sth r4, glob@toc@l(r3)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, 0
   %conv1 = sext i1 %cmp to i16
   store i16 %conv1, i16* @glob
   ret void
-; CHECK-LABEL: @test_llgeus_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: sth [[REG1]]
-; CHECK: blr  
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllgtsll.ll b/test/CodeGen/PowerPC/testComparesllgtsll.ll
index deb9ad5621d02b1c5cd9f45e0a3a316411b5fb80..8948503c3b633e3e7ab9f9d8cb5c9ec20b305dce 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgtsll.ll
+++ b/test/CodeGen/PowerPC/testComparesllgtsll.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,11 +12,11 @@
 define i64 @test_llgtsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -27,12 +28,12 @@ entry:
 define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    sradi r5, r4, 63
+; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    subfc r3, r3, r4
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, %b
@@ -58,9 +59,11 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtsll_sext_z(i64 %a) {
 ; CHECK-LABEL: test_llgtsll_sext_z:
-; CHECK:       addi [[REG1:r[0-9]+]], r3, -1
-; CHECK-NEXT:  nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK-NEXT:  sradi r3, [[REG2]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r4, r3, -1
+; CHECK-NEXT:    nor r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   %conv1 = sext i1 %cmp to i64
@@ -71,12 +74,16 @@ entry:
 define void @test_llgtsll_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT:     neg 
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -88,12 +95,17 @@ entry:
 define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llgtsll_sext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT:    sradi r6, r4, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    adde r3, r3, r6
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK:         neg {{r[0-9]+}}, [[REG5]]
 entry:
   %cmp = icmp sgt i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -123,9 +135,14 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtsll_sext_z_store(i64 %a) {
 ; CHECK-LABEL: test_llgtsll_sext_z_store:
-; CHECK:    addi [[REG1:r[0-9]+]], r3, -1
-; CHECK:    nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK:    sradi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    addi r5, r3, -1
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    nor r3, r5, r3
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    std r3, 0(r4)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   %conv1 = sext i1 %cmp to i64

diff --git a/test/CodeGen/PowerPC/testComparesllgtuc.ll b/test/CodeGen/PowerPC/testComparesllgtuc.ll
index 685026ad03d1cb5b3e122bc677426293a59a2913..b885082190dfd05f26c802f14bdfcca6b323429d 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgtuc.ll
+++ b/test/CodeGen/PowerPC/testComparesllgtuc.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llgtuc:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -22,8 +24,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llgtuc_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -34,9 +37,10 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtuc_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_llgtuc_z:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 0
@@ -47,10 +51,11 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtuc_sext_z(i8 zeroext %a) {
 ; CHECK-LABEL: test_llgtuc_sext_z:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    neg r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 0
@@ -61,8 +66,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llgtuc_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stb r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -73,8 +83,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llgtuc_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stb r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
   %conv3 = sext i1 %cmp to i8
@@ -85,10 +100,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtuc_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_llgtuc_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    stb r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 0
@@ -100,11 +118,14 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtuc_sext_z_store(i8 zeroext %a) {
 ; CHECK-LABEL: test_llgtuc_sext_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    neg r3, r3
-; CHECK:    stb r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i8 %a, 0

diff --git a/test/CodeGen/PowerPC/testComparesllgtui.ll b/test/CodeGen/PowerPC/testComparesllgtui.ll
index a1c8777e3832a473491f17f735a00acd66e4b707..4a093db0b9cd7f43fe9da5bbaee567c9ab646cad 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgtui.ll
+++ b/test/CodeGen/PowerPC/testComparesllgtui.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,9 +11,10 @@
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llgtui:
-; CHECK-NOT:     clrldi
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -22,8 +24,9 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llgtui_sext:
-; CHECK:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
@@ -34,7 +37,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtui_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_llgtui_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
@@ -47,7 +51,8 @@ entry:
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llgtui_sext_z(i32 zeroext %a) {
 ; CHECK-LABEL: test_llgtui_sext_z:
-; CHECK:    cntlzw r3, r3
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    neg r3, r3
@@ -61,8 +66,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llgtui_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -73,8 +83,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llgtui_sext_store:
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -85,10 +100,13 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtui_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llgtui_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    stw r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, 0
@@ -100,11 +118,14 @@ entry:
 ; Function Attrs: norecurse nounwind
 define void @test_llgtui_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llgtui_sext_z_store:
-; CHECK:    cntlzw r3, r3
-; CHECK:    srwi r3, r3, 5
-; CHECK:    xori r3, r3, 1
-; CHECK:    neg r3, r3
-; CHECK:    stw r3, 0(r4)
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ne i32 %a, 0

diff --git a/test/CodeGen/PowerPC/testComparesllgtus.ll b/test/CodeGen/PowerPC/testComparesllgtus.ll
index 94bb145460642d9c9ea1fc8549e2d4c944729607..b148c6861440ec9bda2344f4196a5b71d8f6119a 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllgtus.ll
+++ b/test/CodeGen/PowerPC/testComparesllgtus.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
 define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -24,8 +25,8 @@ entry:
 define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -66,8 +67,12 @@ entry:
 define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    sth r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -79,8 +84,12 @@ entry:
 define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llgtus_sext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r4, r3
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    sth r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
   %conv3 = sext i1 %cmp to i16

diff --git a/test/CodeGen/PowerPC/testComparesllleuc.ll b/test/CodeGen/PowerPC/testComparesllleuc.ll
index b2df0167f4864147144fac07a56c1d73856fa620..f54027714da3b87dabc7b15bb358ebf38b1322b8 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllleuc.ll
+++ b/test/CodeGen/PowerPC/testComparesllleuc.ll
@@ -1,116 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llleuc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: test_llleuc:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llleuc_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: @test_llleuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llleuc_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, 0
   %conv2 = zext i1 %cmp to i64
   ret i64 %conv2
-; CHECK-LABEL: test_llleuc_z:
-; CHECK: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llleuc_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, 0
   %conv2 = sext i1 %cmp to i64
   ret i64 %conv2
-; CHECK-LABEL: @test_llleuc_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llleuc_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleuc_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = zext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK-LABEL: test_llleuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llleuc_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleuc_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
   %conv3 = sext i1 %cmp to i8
   store i8 %conv3, i8* @glob
   ret void
-; CHECK-LABEL: @test_llleuc_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stb  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llleuc_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleuc_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    stb r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, 0
   %conv2 = zext i1 %cmp to i8
   store i8 %conv2, i8* @glob
   ret void
-; CHECK-LABEL: test_llleuc_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi {{r[0-9]}}, r3, 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llleuc_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    stb r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleuc_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    stb r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, 0
   %conv2 = sext i1 %cmp to i8
   store i8 %conv2, i8* @glob
   ret void
-; CHECK-LABEL: @test_llleuc_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stb [[REG3]]
-; CHECK: blr
 }

diff --git a/test/CodeGen/PowerPC/testComparesllleui.ll b/test/CodeGen/PowerPC/testComparesllleui.ll
index fa77495d7e548082ec15f0c5141e2272dabdd4a8..d6bf2e26e1e9ff3ce727d2d8480430fd81820101 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllleui.ll
+++ b/test/CodeGen/PowerPC/testComparesllleui.ll
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i32 0, align 4
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llleui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: test_llleui:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llleui_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llleui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llleui_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, 0
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: test_llleui_z:
-; CHECK: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llleui_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llleui_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llleui_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleui_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
-; CHECK-LABEL: test_llleui_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llleui_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleui_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    stw r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_llleui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llleui_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleui_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    stw r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, 0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @glob
   ret void
-; CHECK-LABEL: test_llleui_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llleui_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    stw r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleui_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    stw r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, 0
   %sub = sext i1 %cmp to i32
   store i32 %sub, i32* @glob
   ret void
-; CHECK-LABEL: @test_llleui_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stw [[REG3]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllleull.ll b/test/CodeGen/PowerPC/testComparesllleull.ll
index bd75f8c736bee3b22a7779074dc69da50307cf8f..2eca70ed014c728312fe1f48c8f4a464ac8dc27c 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllleull.ll
+++ b/test/CodeGen/PowerPC/testComparesllleull.ll
@@ -1,115 +1,170 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i64 0, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llleull:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: test_llleull:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llleull_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    subfc r4, r3, r4
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llleull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleull_z(i64 %a) {
+; CHECK-LABEL: test_llleull_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = zext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: test_llleull_z
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleull_sext_z(i64 %a) {
+; CHECK-LABEL: test_llleull_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addic r3, r3, -1
+; CHECK-NEXT:    subfe r3, r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK-LABEL: @test_llleull_sext_z
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe r3, [[REG1]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llleull_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r3, r3, r3
+; BE-NEXT:    addi r3, r3, 1
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleull_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r3, r3
+; LE-NEXT:    addi r3, r3, 1
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: test_llleull_store:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK: addi r3, [[REG1]], 1
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llleull_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r4, r3, r4
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    subfe r3, r3, r3
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleull_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    subfc r4, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r3, r3
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, %b
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_llleull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleull_z_store(i64 %a) {
+; BE-LABEL: test_llleull_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzd r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    rldicl r3, r3, 58, 63
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleull_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzd r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 58, 63
+; LE-NEXT:    std r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = zext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: test_llleull_z_store:
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleull_sext_z_store(i64 %a) {
+; BE-LABEL: test_llleull_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    addic r3, r3, -1
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    subfe r3, r3, r3
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleull_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addic r3, r3, -1
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    subfe r3, r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
   %conv1 = sext i1 %cmp to i64
   store i64 %conv1, i64* @glob
   ret void
-; CHECK-LABEL: @test_llleull_sext_z_store
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: std [[REG2]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllleus.ll b/test/CodeGen/PowerPC/testComparesllleus.ll
index 51ebb5e572d9b0ae57fcb72454dd106cc1391291..1cdb66d6cff81eadcf74000429991420809d1f73 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllleus.ll
+++ b/test/CodeGen/PowerPC/testComparesllleus.ll
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llleus:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    not r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = zext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: test_llleus:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llleus_sext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sub r3, r4, r3
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    addi r3, r3, -1
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = sext i1 %cmp to i64
   ret i64 %conv3
-; CHECK-LABEL: @test_llleus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llleus_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = zext i1 %cmp to i64
   ret i64 %conv2
-; CHECK-LABEL: test_llleus_z:
-; CHECK: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @test_llleus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llleus_sext_z:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cntlzw r3, r3
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    neg r3, r3
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = sext i1 %cmp to i64
   ret i64 %conv2
-; CHECK-LABEL: @test_llleus_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llleus_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    not r3, r3
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleus_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    not r3, r3
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = zext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: test_llleus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llleus_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r4, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    addi r3, r3, -1
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleus_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r4, r3
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    addi r3, r3, -1
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
   %conv3 = sext i1 %cmp to i16
   store i16 %conv3, i16* @glob
   ret void
-; CHECK-LABEL: @test_llleus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth  [[REG3]]
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llleus_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleus_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    sth r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = zext i1 %cmp to i16
   store i16 %conv2, i16* @glob
   ret void
-; CHECK-LABEL: test_llleus_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind
 define void @test_llleus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llleus_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    cntlzw r3, r3
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    srwi r3, r3, 5
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    sth r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llleus_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    cntlzw r3, r3
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    srwi r3, r3, 5
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    sth r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, 0
   %conv2 = sext i1 %cmp to i16
   store i16 %conv2, i16* @glob
   ret void
-; CHECK-LABEL: @test_llleus_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: sth [[REG3]]
-; CHECK: blr
 }
 

diff --git a/test/CodeGen/PowerPC/testComparesllltsll.ll b/test/CodeGen/PowerPC/testComparesllltsll.ll
index 3e37daf046f02b1d8e4020ba85262721965f0db5..5bf437c920642f70a50e21975ee0d8107eccf959 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllltsll.ll
+++ b/test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i64 0, align 8
 
@@ -12,11 +14,11 @@
 define i64 @test_llltsll(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llltsll:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori r3, [[REG4]], 1
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -28,12 +30,12 @@ entry:
 define i64 @test_llltsll_sext(i64 %a, i64 %b) {
 ; CHECK-LABEL: test_llltsll_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT:    neg r3, [[REG5]]
+; CHECK-NEXT:    sradi r5, r3, 63
+; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    subfc r3, r4, r3
+; CHECK-NEXT:    adde r3, r6, r5
+; CHECK-NEXT:    xori r3, r3, 1
+; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, %b
@@ -55,14 +57,29 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_llltsll_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llltsll_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_llltsll_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    sradi r6, r3, 63
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    adde r3, r3, r6
+; BE-NEXT:    xori r3, r3, 1
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llltsll_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sradi r6, r3, 63
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    adde r3, r3, r6
+; LE-NEXT:    xori r3, r3, 1
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT:     neg
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = zext i1 %cmp to i64
@@ -72,14 +89,31 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_llltsll_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llltsll_sext_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_llltsll_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    sradi r6, r3, 63
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    subfc r3, r4, r3
+; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    ld r4, .LC0@toc@l(r5)
+; BE-NEXT:    adde r3, r3, r6
+; BE-NEXT:    xori r3, r3, 1
+; BE-NEXT:    neg r3, r3
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llltsll_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sradi r6, r3, 63
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    subfc r3, r4, r3
+; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    adde r3, r3, r6
+; LE-NEXT:    xori r3, r3, 1
+; LE-NEXT:    neg r3, r3
+; LE-NEXT:    std r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 ; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK:         neg {{r[0-9]+}}, [[REG5]]
 entry:
   %cmp = icmp slt i64 %a, %b
   %conv1 = sext i1 %cmp to i64
@@ -89,8 +123,20 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_llltsll_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_llltsll_sext_z_store:
-; CHECK:    sradi r3, r3, 63
+; BE-LABEL: test_llltsll_sext_z_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r4, r2, .LC0@toc@ha
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    ld r4, .LC0@toc@l(r4)
+; BE-NEXT:    std r3, 0(r4)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llltsll_sext_z_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    addis r4, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    std r3, glob@toc@l(r4)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 0
   %sub = sext i1 %cmp to i64

diff --git a/test/CodeGen/PowerPC/testComparesllltuc.ll b/test/CodeGen/PowerPC/testComparesllltuc.ll
index a8244e757b15d2b5b9a5e5fea48c1a8841ee8d02..47d196720c62daeae29a14b1439de4e215c81fc7 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllltuc.ll
+++ b/test/CodeGen/PowerPC/testComparesllltuc.ll
@@ -1,9 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i8 0, align 1
 
@@ -11,8 +14,8 @@
 define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llltuc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -24,8 +27,8 @@ entry:
 define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test_llltuc_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -35,10 +38,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_llltuc_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[2-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_llltuc_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    stb r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llltuc_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = zext i1 %cmp to i8
@@ -48,10 +63,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_llltuc_sext_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_llltuc_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    stb r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llltuc_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    stb r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
   %conv3 = sext i1 %cmp to i8

diff --git a/test/CodeGen/PowerPC/testComparesllltui.ll b/test/CodeGen/PowerPC/testComparesllltui.ll
index 126d110d04cb99fbcf6d420fc21d7796de8a0d25..3f5dfba99e883a49c82108c72d2a8b8babcb319c 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllltui.ll
+++ b/test/CodeGen/PowerPC/testComparesllltui.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,9 +12,8 @@
 define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NOT:     clrldi
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -25,8 +25,8 @@ entry:
 define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -58,9 +58,12 @@ entry:
 define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NOT:     clrldi
-; CHECK:         sub [[REG:r[2-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -72,9 +75,12 @@ entry:
 define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
 ; CHECK-LABEL: test_llltui_sext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NOT:     clrldi
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
+; CHECK-NEXT:    sradi r3, r3, 63
+; CHECK-NEXT:    stw r3, 0(r5)
+; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
   %sub = sext i1 %cmp to i32
@@ -86,8 +92,10 @@ entry:
 define void @test_llltui_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llltui_z_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         li [[REG:r[0-9]+]], 0
-; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-NEXT:    stw r4, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   store i32 0, i32* @glob, align 4
@@ -98,8 +106,10 @@ entry:
 define void @test_llltui_sext_z_store(i32 zeroext %a) {
 ; CHECK-LABEL: test_llltui_sext_z_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:         li [[REG:r[0-9]+]], 0
-; CHECK:         stw [[REG]], 0(r3)
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-NEXT:    stw r4, 0(r3)
 ; CHECK-NEXT:    blr
 entry:
   store i32 0, i32* @glob, align 4

diff --git a/test/CodeGen/PowerPC/testComparesllltus.ll b/test/CodeGen/PowerPC/testComparesllltus.ll
index e997d0aa8b82b644468f79e6bff0fa0cd3e7af00..2cbc1b16c84bd3d4adab435d57cb73d4037cdb21 100644 (file)
--- a/test/CodeGen/PowerPC/testComparesllltus.ll
+++ b/test/CodeGen/PowerPC/testComparesllltus.ll
@@ -1,9 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN:  --check-prefixes=CHECK,LE
 
 @glob = common local_unnamed_addr global i16 0, align 2
 
@@ -11,8 +14,8 @@
 define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llltus:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
@@ -24,8 +27,8 @@ entry:
 define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: test_llltus_sext:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT:    sradi r3, [[REG]], 63
+; CHECK-NEXT:    sub r3, r3, r4
+; CHECK-NEXT:    sradi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
@@ -35,9 +38,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_llltus_store:
-; CHECK:         sub [[REG:r[2-9]+]], r3, r4
-; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_llltus_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    sth r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llltus_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = zext i1 %cmp to i16
@@ -47,10 +63,22 @@ entry:
 
 ; Function Attrs: norecurse nounwind
 define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_llltus_sext_store:
-; CHECK:       # %bb.0: # %entry
-; CHECK:         sub [[REG:r[0-9]+]], r3, r4
-; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_llltus_sext_store:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    addis r5, r2, .LC0@toc@ha
+; BE-NEXT:    sub r3, r3, r4
+; BE-NEXT:    ld r5, .LC0@toc@l(r5)
+; BE-NEXT:    sradi r3, r3, 63
+; BE-NEXT:    sth r3, 0(r5)
+; BE-NEXT:    blr
+;
+; LE-LABEL: test_llltus_sext_store:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    sub r3, r3, r4
+; LE-NEXT:    addis r5, r2, glob@toc@ha
+; LE-NEXT:    sradi r3, r3, 63
+; LE-NEXT:    sth r3, glob@toc@l(r5)
+; LE-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
   %conv3 = sext i1 %cmp to i16

diff --git a/test/CodeGen/PowerPC/vec_shuffle.ll b/test/CodeGen/PowerPC/vec_shuffle.ll
index 2ae98fcf09aaaf03a92a0a21f718f92848d6e895..40885f80310e0b00a6b6d6f3a80dc08c36f371ea 100644 (file)
--- a/test/CodeGen/PowerPC/vec_shuffle.ll
+++ b/test/CodeGen/PowerPC/vec_shuffle.ll
@@ -1,13 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: opt -mtriple=powerpc-unknown-linux-gnu < %s -instcombine | \
 ; RUN:   llc -mtriple=ppc32-- -mcpu=g5 | not grep vperm
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 > %t
-; RUN: grep vsldoi  %t | count 2
-; RUN: grep vmrgh   %t | count 7
-; RUN: grep vmrgl   %t | count 6
-; RUN: grep vpkuhum %t | count 1
-; RUN: grep vpkuwum %t | count 1
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | FileCheck %s
 
 define void @VSLDOI_xy(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VSLDOI_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vsldoi 2, 2, 3, 5
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=1]
        %tmp2 = load <8 x i16>, <8 x i16>* %B           ; <<8 x i16>> [#uses=1]
@@ -51,6 +54,12 @@ entry:
 }
 
 define void @VSLDOI_xx(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VSLDOI_xx:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vsldoi 2, 2, 2, 5
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=1]
        %tmp2 = load <8 x i16>, <8 x i16>* %A           ; <<8 x i16>> [#uses=1]
        %tmp.upgrd.5 = bitcast <8 x i16> %tmp to <16 x i8>              ; <<16 x i8>> [#uses=11]
@@ -93,6 +102,14 @@ define void @VSLDOI_xx(<8 x i16>* %A, <8 x i16>* %B) {
 }
 
 define void @VPERM_promote(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VPERM_promote:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vspltisb 4, 14
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vperm 2, 2, 3, 4
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=1]
        %tmp.upgrd.9 = bitcast <8 x i16> %tmp to <4 x i32>              ; <<4 x i32>> [#uses=1]
@@ -107,6 +124,13 @@ entry:
 declare <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>, <4 x i32>, <16 x i8>)
 
 define void @tb_l(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: tb_l:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrglb 2, 2, 3
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <16 x i8>, <16 x i8>* %A            ; <<16 x i8>> [#uses=8]
        %tmp2 = load <16 x i8>, <16 x i8>* %B           ; <<16 x i8>> [#uses=8]
@@ -147,6 +171,13 @@ entry:
 }
 
 define void @th_l(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: th_l:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrglh 2, 2, 3
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=4]
        %tmp2 = load <8 x i16>, <8 x i16>* %B           ; <<8 x i16>> [#uses=4]
@@ -171,6 +202,13 @@ entry:
 }
 
 define void @tw_l(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: tw_l:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrglw 2, 2, 3
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <4 x i32>, <4 x i32>* %A            ; <<4 x i32>> [#uses=2]
        %tmp2 = load <4 x i32>, <4 x i32>* %B           ; <<4 x i32>> [#uses=2]
@@ -187,6 +225,13 @@ entry:
 }
 
 define void @tb_h(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: tb_h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrghb 2, 2, 3
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <16 x i8>, <16 x i8>* %A            ; <<16 x i8>> [#uses=8]
        %tmp2 = load <16 x i8>, <16 x i8>* %B           ; <<16 x i8>> [#uses=8]
@@ -227,6 +272,13 @@ entry:
 }
 
 define void @th_h(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: th_h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrghh 2, 2, 3
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=4]
        %tmp2 = load <8 x i16>, <8 x i16>* %B           ; <<8 x i16>> [#uses=4]
@@ -251,6 +303,13 @@ entry:
 }
 
 define void @tw_h(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: tw_h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrghw 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <4 x i32>, <4 x i32>* %A            ; <<4 x i32>> [#uses=2]
        %tmp2 = load <4 x i32>, <4 x i32>* %B           ; <<4 x i32>> [#uses=2]
@@ -267,6 +326,13 @@ entry:
 }
 
 define void @tw_h_flop(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: tw_h_flop:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrghw 2, 2, 3
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
        %tmp = load <4 x i32>, <4 x i32>* %A            ; <<4 x i32>> [#uses=2]
        %tmp2 = load <4 x i32>, <4 x i32>* %B           ; <<4 x i32>> [#uses=2]
        %tmp.upgrd.18 = extractelement <4 x i32> %tmp, i32 0            ; <i32> [#uses=1]
@@ -282,6 +348,12 @@ define void @tw_h_flop(<4 x i32>* %A, <4 x i32>* %B) {
 }
 
 define void @VMRG_UNARY_tb_l(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tb_l:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrglb 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <16 x i8>, <16 x i8>* %A            ; <<16 x i8>> [#uses=16]
        %tmp.upgrd.19 = extractelement <16 x i8> %tmp, i32 8            ; <i8> [#uses=1]
@@ -321,6 +393,12 @@ entry:
 }
 
 define void @VMRG_UNARY_th_l(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VMRG_UNARY_th_l:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrglh 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=8]
        %tmp.upgrd.20 = extractelement <8 x i16> %tmp, i32 4            ; <i16> [#uses=1]
@@ -344,6 +422,12 @@ entry:
 }
 
 define void @VMRG_UNARY_tw_l(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tw_l:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrglw 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <4 x i32>, <4 x i32>* %A            ; <<4 x i32>> [#uses=4]
        %tmp.upgrd.21 = extractelement <4 x i32> %tmp, i32 2            ; <i32> [#uses=1]
@@ -359,6 +443,12 @@ entry:
 }
 
 define void @VMRG_UNARY_tb_h(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tb_h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrghb 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <16 x i8>, <16 x i8>* %A            ; <<16 x i8>> [#uses=16]
        %tmp.upgrd.22 = extractelement <16 x i8> %tmp, i32 0            ; <i8> [#uses=1]
@@ -398,6 +488,12 @@ entry:
 }
 
 define void @VMRG_UNARY_th_h(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VMRG_UNARY_th_h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrghh 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=8]
        %tmp.upgrd.23 = extractelement <8 x i16> %tmp, i32 0            ; <i16> [#uses=1]
@@ -421,6 +517,12 @@ entry:
 }
 
 define void @VMRG_UNARY_tw_h(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tw_h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrghw 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <4 x i32>, <4 x i32>* %A            ; <<4 x i32>> [#uses=4]
        %tmp.upgrd.24 = extractelement <4 x i32> %tmp, i32 0            ; <i32> [#uses=1]
@@ -436,6 +538,12 @@ entry:
 }
 
 define void @VPCKUHUM_unary(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VPCKUHUM_unary:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vpkuhum 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <8 x i16>, <8 x i16>* %A            ; <<8 x i16>> [#uses=2]
        %tmp.upgrd.25 = bitcast <8 x i16> %tmp to <16 x i8>             ; <<16 x i8>> [#uses=8]
@@ -478,6 +586,12 @@ entry:
 }
 
 define void @VPCKUWUM_unary(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: VPCKUWUM_unary:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vpkuwum 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <4 x i32>, <4 x i32>* %A            ; <<4 x i32>> [#uses=2]
        %tmp.upgrd.28 = bitcast <4 x i32> %tmp to <8 x i16>             ; <<8 x i16>> [#uses=4]

diff --git a/test/CodeGen/PowerPC/vec_shuffle_le.ll b/test/CodeGen/PowerPC/vec_shuffle_le.ll
index be79ea9fb73e28090fa84e4b617ea4677a9479a5..2d456d06b2586502064a79ae76edbae4275d8475 100644 (file)
--- a/test/CodeGen/PowerPC/vec_shuffle_le.ll
+++ b/test/CodeGen/PowerPC/vec_shuffle_le.ll
@@ -1,208 +1,272 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
 
 define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VPKUHUM_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vpkuhum 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VPKUHUM_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vpkuhum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VPKUHUM_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VPKUHUM_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vpkuhum 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VPKUHUM_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
-; CHECK: vpkuhum
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VPKUWUM_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vpkuwum 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VPKUWUM_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vpkuwum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VPKUWUM_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VPKUWUM_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vpkuwum 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VPKUWUM_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
-; CHECK: vpkuwum
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGLB_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrglb 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGLB_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGLB_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGLB_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrglb 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGLB_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
-; CHECK: vmrglb
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGHB_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrghb 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGHB_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGHB_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGHB_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrghb 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGHB_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
-; CHECK: vmrghb
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGLH_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrglh 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGLH_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGLH_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGLH_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrglh 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGLH_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
-; CHECK: vmrglh
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGHH_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrghh 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGHH_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGHH_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGHH_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrghh 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGHH_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
-; CHECK: vmrghh
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGLW_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrglw 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGLW_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGLW_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGLW_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrglw 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGLW_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
-; CHECK: vmrglw
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGHW_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vmrghw 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGHW_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VMRGHW_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGHW_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vmrghw 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VMRGHW_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
-; CHECK: vmrghw
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }
 
 define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VSLDOI_xy:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vsldoi 2, 3, 2, 4
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VSLDOI_xy:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = load <16 x i8>, <16 x i8>* %B
         %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vsldoi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 4
         store <16 x i8> %tmp3, <16 x i8>* %A
         ret void
 }
 
 define void @VSLDOI_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VSLDOI_xx:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vsldoi 2, 2, 2, 4
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
-; CHECK: VSLDOI_xx:
         %tmp = load <16 x i8>, <16 x i8>* %A
         %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
-; CHECK: vsldoi {{[0-9]+}}, [[REG1:[0-9]+]], [[REG1]], 4
         store <16 x i8> %tmp2, <16 x i8>* %A
         ret void
 }

diff --git a/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll b/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
index e1be6663a1302805c8c358e9222c76cd5fd70872..33226e8a08560bedb564d4e2f0d7f211f6511707 100644 (file)
--- a/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
+++ b/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
@@ -1,7 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s
 
 define void @VPKUDUM_unary(<2 x i64>* %A) {
+; CHECK-LABEL: VPKUDUM_unary:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvw4x 34, 0, 3
+; CHECK-NEXT:    vpkudum 2, 2, 2
+; CHECK-NEXT:    stxvw4x 34, 0, 3
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: VPKUDUM_unary:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    lxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT:    vmrglw 3, 2, 2
+; CHECK-PWR7-NEXT:    vmrghw 2, 2, 2
+; CHECK-PWR7-NEXT:    vmrglw 2, 2, 3
+; CHECK-PWR7-NEXT:    stxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT:    blr
 entry:
         %tmp = load <2 x i64>, <2 x i64>* %A
         %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -16,16 +32,24 @@ entry:
         ret void
 }
 
-; CHECK-LABEL: @VPKUDUM_unary
-; CHECK-NOT:   vperm
-; CHECK-NOT:   vmrglw
-; CHECK-NOT:   vmrghw
-; CHECK:       vpkudum
-; CHECK-PWR7:  vmrglw
-; CHECK-PWR7:  vmrghw
-; CHECK-PWR7:  vmrglw
-
 define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
+; CHECK-LABEL: VPKUDUM:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxvw4x 34, 0, 3
+; CHECK-NEXT:    lxvw4x 35, 0, 4
+; CHECK-NEXT:    vpkudum 2, 2, 3
+; CHECK-NEXT:    stxvw4x 34, 0, 3
+; CHECK-NEXT:    blr
+;
+; CHECK-PWR7-LABEL: VPKUDUM:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    lxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT:    lxvw4x 35, 0, 4
+; CHECK-PWR7-NEXT:    vmrglw 4, 2, 3
+; CHECK-PWR7-NEXT:    vmrghw 2, 2, 3
+; CHECK-PWR7-NEXT:    vmrglw 2, 2, 4
+; CHECK-PWR7-NEXT:    stxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT:    blr
 entry:
         %tmp = load <2 x i64>, <2 x i64>* %A
         %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -44,11 +68,3 @@ entry:
         ret void
 }
 
-; CHECK-LABEL: @VPKUDUM
-; CHECK-NOT:   vperm
-; CHECK-NOT:   vmrglw
-; CHECK-NOT:   vmrghw
-; CHECK:       vpkudum
-; CHECK-PWR7:  vmrglw
-; CHECK-PWR7:  vmrghw
-; CHECK-PWR7:  vmrglw

diff --git a/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll b/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
index df373aef4c0316cff5ba68b6b7f88d9df9b6a595..65200298e3a1e4acad714b0e776f5366b4c3e448 100644 (file)
--- a/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
+++ b/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
@@ -1,6 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
 
 define void @VPKUDUM_unary(<2 x i64>* %A) {
+; CHECK-LABEL: VPKUDUM_unary:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    vpkudum 2, 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <2 x i64>, <2 x i64>* %A
        %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -15,11 +22,14 @@ entry:
        ret void
 }
 
-; CHECK-LABEL: @VPKUDUM_unary
-; CHECK-NOT:   vperm
-; CHECK:       vpkudum
-
 define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
+; CHECK-LABEL: VPKUDUM:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lvx 2, 0, 3
+; CHECK-NEXT:    lvx 3, 0, 4
+; CHECK-NEXT:    vpkudum 2, 3, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    blr
 entry:
        %tmp = load <2 x i64>, <2 x i64>* %A
        %tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -38,6 +48,3 @@ entry:
        ret void
 }
 
-; CHECK-LABEL: @VPKUDUM
-; CHECK-NOT:   vperm
-; CHECK:       vpkudum