[AMDGPU] Ban i8 min3 promotion.

I found this really weird WWM-related case whereby through the WWM
transformations our isel lowering was trying to promote 2 min's into a
min3 for the i8 type, which our hardware doesn't support.

The new min3_i8.ll test case would previously spew the error:

PromoteIntegerResult #0: t69: i8 = SMIN3 t70, Constant:i8<0>, t68

Before the simple fix to our isel lowering to not do it for i8 MVT's.

Differential Revision: https://reviews.llvm.org/D59543

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356464 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp
index 38f27c5ec654ee909465747c08da3a50ef43d0bf..0aca05bf1d8cd710a37da07b8830fcc92b9a19b6 100644 (file)
--- a/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8137,10 +8137,10 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
   // Only do this if the inner op has one use since this will just increases
   // register pressure for no benefit.
 
-
   if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
-      !VT.isVector() && VT != MVT::f64 &&
-      ((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) {
+      !VT.isVector() &&
+      (VT == MVT::i32 || VT == MVT::f32 ||
+       ((VT == MVT::f16 || VT == MVT::i16) && Subtarget->hasMin3Max3_16()))) {
     // max(max(a, b), c) -> max3(a, b, c)
     // min(min(a, b), c) -> min3(a, b, c)
     if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {

diff --git a/test/CodeGen/AMDGPU/fmin3.ll b/test/CodeGen/AMDGPU/fmin3.ll
index 48d0eedba5b955479a469c934065236cc5386ed2..0c3b04d55d246cfef6d9d34a42548796d6751474 100644 (file)
--- a/test/CodeGen/AMDGPU/fmin3.ll
+++ b/test/CodeGen/AMDGPU/fmin3.ll
@@ -118,7 +118,33 @@ entry:
   ret <2 x half> %res
 }
 
+; GCN-LABEL: {{^}}test_fmin3_olt_0_f64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @test_fmin3_olt_0_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) #0 {
+  %a = load volatile double, double addrspace(1)* %aptr, align 4
+  %b = load volatile double, double addrspace(1)* %bptr, align 4
+  %c = load volatile double, double addrspace(1)* %cptr, align 4
+  %f0 = call double @llvm.minnum.f64(double %a, double %b)
+  %f1 = call double @llvm.minnum.f64(double %f0, double %c)
+  store double %f1, double addrspace(1)* %out, align 4
+  ret void
+}
+
+; Commute operand of second fmin
+; GCN-LABEL: {{^}}test_fmin3_olt_1_f64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @test_fmin3_olt_1_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) #0 {
+  %a = load volatile double, double addrspace(1)* %aptr, align 4
+  %b = load volatile double, double addrspace(1)* %bptr, align 4
+  %c = load volatile double, double addrspace(1)* %cptr, align 4
+  %f0 = call double @llvm.minnum.f64(double %a, double %b)
+  %f1 = call double @llvm.minnum.f64(double %c, double %f0)
+  store double %f1, double addrspace(1)* %out, align 4
+  ret void
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
+declare double @llvm.minnum.f64(double, double) #1
 declare float @llvm.minnum.f32(float, float) #1
 declare half @llvm.minnum.f16(half, half) #1
 declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)

diff --git a/test/CodeGen/AMDGPU/max3.ll b/test/CodeGen/AMDGPU/max3.ll
index 46dcf8e340f47450af01accaf24934876c72122d..4dc5d484e167316c4fa101311b2ecfeb579e8783 100644 (file)
--- a/test/CodeGen/AMDGPU/max3.ll
+++ b/test/CodeGen/AMDGPU/max3.ll
@@ -88,6 +88,178 @@ define amdgpu_kernel void @v_test_umax3_ugt_i16(i16 addrspace(1)* %out, i16 addr
   ret void
 }
 
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i8:
+; SI: v_max3_i32
+
+; VI: v_max_i16
+; VI: v_max_i16
+
+; GFX9: v_max3_i16
+define amdgpu_kernel void @v_test_imax3_sgt_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %a = load i8, i8 addrspace(1)* %gep0
+  %b = load i8, i8 addrspace(1)* %gep1
+  %c = load i8, i8 addrspace(1)* %gep2
+  %icmp0 = icmp sgt i8 %a, %b
+  %i0 = select i1 %icmp0, i8 %a, i8 %b
+  %icmp1 = icmp sgt i8 %i0, %c
+  %i1 = select i1 %icmp1, i8 %i0, i8 %c
+  store i8 %i1, i8 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i8:
+; SI: v_max3_u32
+
+; VI: v_max_u16
+; VI: v_max_u16
+
+; GFX9: v_max3_u16
+define amdgpu_kernel void @v_test_umax3_ugt_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %a = load i8, i8 addrspace(1)* %gep0
+  %b = load i8, i8 addrspace(1)* %gep1
+  %c = load i8, i8 addrspace(1)* %gep2
+  %icmp0 = icmp ugt i8 %a, %b
+  %i0 = select i1 %icmp0, i8 %a, i8 %b
+  %icmp1 = icmp ugt i8 %i0, %c
+  %i1 = select i1 %icmp1, i8 %i0, i8 %c
+  store i8 %i1, i8 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i7:
+; SI: v_max3_i32
+
+; VI: v_max_i16
+; VI: v_max_i16
+
+; GFX9: v_max3_i16
+define amdgpu_kernel void @v_test_imax3_sgt_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+  %a = load i7, i7 addrspace(1)* %gep0
+  %b = load i7, i7 addrspace(1)* %gep1
+  %c = load i7, i7 addrspace(1)* %gep2
+  %icmp0 = icmp sgt i7 %a, %b
+  %i0 = select i1 %icmp0, i7 %a, i7 %b
+  %icmp1 = icmp sgt i7 %i0, %c
+  %i1 = select i1 %icmp1, i7 %i0, i7 %c
+  store i7 %i1, i7 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i7:
+; SI: v_max3_u32
+
+; VI: v_max_u16
+; VI: v_max_u16
+
+; GFX9: v_max3_u16
+define amdgpu_kernel void @v_test_umax3_ugt_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+  %a = load i7, i7 addrspace(1)* %gep0
+  %b = load i7, i7 addrspace(1)* %gep1
+  %c = load i7, i7 addrspace(1)* %gep2
+  %icmp0 = icmp ugt i7 %a, %b
+  %i0 = select i1 %icmp0, i7 %a, i7 %b
+  %icmp1 = icmp ugt i7 %i0, %c
+  %i1 = select i1 %icmp1, i7 %i0, i7 %c
+  store i7 %i1, i7 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i33:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_imax3_sgt_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+  %a = load i33, i33 addrspace(1)* %gep0
+  %b = load i33, i33 addrspace(1)* %gep1
+  %c = load i33, i33 addrspace(1)* %gep2
+  %icmp0 = icmp sgt i33 %a, %b
+  %i0 = select i1 %icmp0, i33 %a, i33 %b
+  %icmp1 = icmp sgt i33 %i0, %c
+  %i1 = select i1 %icmp1, i33 %i0, i33 %c
+  store i33 %i1, i33 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i33:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_umax3_ugt_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+  %a = load i33, i33 addrspace(1)* %gep0
+  %b = load i33, i33 addrspace(1)* %gep1
+  %c = load i33, i33 addrspace(1)* %gep2
+  %icmp0 = icmp ugt i33 %a, %b
+  %i0 = select i1 %icmp0, i33 %a, i33 %b
+  %icmp1 = icmp ugt i33 %i0, %c
+  %i1 = select i1 %icmp1, i33 %i0, i33 %c
+  store i33 %i1, i33 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i64:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_imax3_sgt_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %gep0
+  %b = load i64, i64 addrspace(1)* %gep1
+  %c = load i64, i64 addrspace(1)* %gep2
+  %icmp0 = icmp sgt i64 %a, %b
+  %i0 = select i1 %icmp0, i64 %a, i64 %b
+  %icmp1 = icmp sgt i64 %i0, %c
+  %i1 = select i1 %icmp1, i64 %i0, i64 %c
+  store i64 %i1, i64 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i64:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_umax3_ugt_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %gep0
+  %b = load i64, i64 addrspace(1)* %gep1
+  %c = load i64, i64 addrspace(1)* %gep2
+  %icmp0 = icmp ugt i64 %a, %b
+  %i0 = select i1 %icmp0, i64 %a, i64 %b
+  %icmp1 = icmp ugt i64 %i0, %c
+  %i1 = select i1 %icmp1, i64 %i0, i64 %c
+  store i64 %i1, i64 addrspace(1)* %out
+  ret void
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 attributes #0 = { nounwind }

diff --git a/test/CodeGen/AMDGPU/min3.ll b/test/CodeGen/AMDGPU/min3.ll
index e20fb81f2ecf412f5ee65227959a9f2a88a4aca7..1e82aca0099d005c9e076a51866e025492fd3a2e 100644 (file)
--- a/test/CodeGen/AMDGPU/min3.ll
+++ b/test/CodeGen/AMDGPU/min3.ll
@@ -158,6 +158,178 @@ define amdgpu_kernel void @v_test_umin3_ult_i16(i16 addrspace(1)* %out, i16 addr
   ret void
 }
 
+; GCN-LABEL: {{^}}v_test_imin3_slt_i8:
+; SI: v_min3_i32
+
+; VI: v_min_i16
+; VI: v_min_i16
+
+; GFX9: v_min3_i16
+define amdgpu_kernel void @v_test_imin3_slt_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %a = load i8, i8 addrspace(1)* %gep0
+  %b = load i8, i8 addrspace(1)* %gep1
+  %c = load i8, i8 addrspace(1)* %gep2
+  %icmp0 = icmp slt i8 %a, %b
+  %i0 = select i1 %icmp0, i8 %a, i8 %b
+  %icmp1 = icmp slt i8 %i0, %c
+  %i1 = select i1 %icmp1, i8 %i0, i8 %c
+  store i8 %i1, i8 addrspace(1)* %outgep
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i8:
+; SI: v_min3_u32
+
+; VI: v_min_u16
+; VI: v_min_u16
+
+; GFX9: v_min3_u16
+define amdgpu_kernel void @v_test_umin3_ult_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+  %a = load i8, i8 addrspace(1)* %gep0
+  %b = load i8, i8 addrspace(1)* %gep1
+  %c = load i8, i8 addrspace(1)* %gep2
+  %icmp0 = icmp ult i8 %a, %b
+  %i0 = select i1 %icmp0, i8 %a, i8 %b
+  %icmp1 = icmp ult i8 %i0, %c
+  %i1 = select i1 %icmp1, i8 %i0, i8 %c
+  store i8 %i1, i8 addrspace(1)* %outgep
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imin3_slt_i7:
+; SI: v_min3_i32
+
+; VI: v_min_i16
+; VI: v_min_i16
+
+; GFX9: v_min3_i16
+define amdgpu_kernel void @v_test_imin3_slt_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+  %a = load i7, i7 addrspace(1)* %gep0
+  %b = load i7, i7 addrspace(1)* %gep1
+  %c = load i7, i7 addrspace(1)* %gep2
+  %icmp0 = icmp slt i7 %a, %b
+  %i0 = select i1 %icmp0, i7 %a, i7 %b
+  %icmp1 = icmp slt i7 %i0, %c
+  %i1 = select i1 %icmp1, i7 %i0, i7 %c
+  store i7 %i1, i7 addrspace(1)* %outgep
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i7:
+; SI: v_min3_u32
+
+; VI: v_min_u16
+; VI: v_min_u16
+
+; GFX9: v_min3_u16
+define amdgpu_kernel void @v_test_umin3_ult_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+  %a = load i7, i7 addrspace(1)* %gep0
+  %b = load i7, i7 addrspace(1)* %gep1
+  %c = load i7, i7 addrspace(1)* %gep2
+  %icmp0 = icmp ult i7 %a, %b
+  %i0 = select i1 %icmp0, i7 %a, i7 %b
+  %icmp1 = icmp ult i7 %i0, %c
+  %i1 = select i1 %icmp1, i7 %i0, i7 %c
+  store i7 %i1, i7 addrspace(1)* %outgep
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imin3_slt_i33:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_imin3_slt_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+  %a = load i33, i33 addrspace(1)* %gep0
+  %b = load i33, i33 addrspace(1)* %gep1
+  %c = load i33, i33 addrspace(1)* %gep2
+  %icmp0 = icmp slt i33 %a, %b
+  %i0 = select i1 %icmp0, i33 %a, i33 %b
+  %icmp1 = icmp slt i33 %i0, %c
+  %i1 = select i1 %icmp1, i33 %i0, i33 %c
+  store i33 %i1, i33 addrspace(1)* %outgep
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i33:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_umin3_ult_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+  %a = load i33, i33 addrspace(1)* %gep0
+  %b = load i33, i33 addrspace(1)* %gep1
+  %c = load i33, i33 addrspace(1)* %gep2
+  %icmp0 = icmp ult i33 %a, %b
+  %i0 = select i1 %icmp0, i33 %a, i33 %b
+  %icmp1 = icmp ult i33 %i0, %c
+  %i1 = select i1 %icmp1, i33 %i0, i33 %c
+  store i33 %i1, i33 addrspace(1)* %outgep
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imin3_slt_i64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_imin3_slt_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %gep0
+  %b = load i64, i64 addrspace(1)* %gep1
+  %c = load i64, i64 addrspace(1)* %gep2
+  %icmp0 = icmp slt i64 %a, %b
+  %i0 = select i1 %icmp0, i64 %a, i64 %b
+  %icmp1 = icmp slt i64 %i0, %c
+  %i1 = select i1 %icmp1, i64 %i0, i64 %c
+  store i64 %i1, i64 addrspace(1)* %outgep
+  ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_umin3_ult_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+  %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+  %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+  %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+  %a = load i64, i64 addrspace(1)* %gep0
+  %b = load i64, i64 addrspace(1)* %gep1
+  %c = load i64, i64 addrspace(1)* %gep2
+  %icmp0 = icmp ult i64 %a, %b
+  %i0 = select i1 %icmp0, i64 %a, i64 %b
+  %icmp1 = icmp ult i64 %i0, %c
+  %i1 = select i1 %icmp1, i64 %i0, i64 %c
+  store i64 %i1, i64 addrspace(1)* %outgep
+  ret void
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 attributes #0 = { nounwind }