[mips][microMIPS] add lapc instruction

Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D35984

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312934 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td
index 45c170950c91089960f04f5c56ef9422aecc2844..23e8b32d489009b8f85dd03ce85c7b66de443b27 100644 (file)
--- a/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -1829,6 +1829,9 @@ def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
                     ISA_MICROMIPS32R6;
 def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
                     ISA_MICROMIPS32R6;
+def : MipsInstAlias<"lapc $rd, $imm",
+                    (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
+                    ISA_MICROMIPS32R6;
 
 //===----------------------------------------------------------------------===//
 //

diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td
index 001d9c1dfae4a78d027b48de31db6d28a9442100..28b911e69be2003ef70a3c763ebc02a6d21d6d71 100644 (file)
--- a/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -950,6 +950,9 @@ def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
 def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
                                            GPR32Opnd:$rt)>, ISA_MIPS32R6;
 
+def : MipsInstAlias<"lapc $rd, $imm",
+                    (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)>, ISA_MIPS32R6;
+
 //===----------------------------------------------------------------------===//
 //
 // Patterns and Pseudo Instructions

diff --git a/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/test/MC/Disassembler/Mips/micromips32r6/valid.txt
index f20d158ac2aaaa8f5f972c7df6fb151015b30e55..f32f2532c24c1763b6c26ccfbcc81ea8c46e00bc 100644 (file)
--- a/test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ b/test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -32,7 +32,7 @@
 0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5
 0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234
 0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5
-0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100
+0x78 0x80 0x00 0x19 # CHECK: lapc $4, 100
 0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
 0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1
 0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2

diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
index 946e8d885bb7ccfea8e2ef74c1966b22355a1072..d586b8043929bc09234010b99c88cadfcf349813 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -1,6 +1,6 @@
 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
-0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
+0x19 0x00 0x80 0xec # CHECK: lapc $4, 100
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56

diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index 7d2d62714c13bd8329a610c674e283969a85fbd1..b2b0dba0b1c6722e46134c4f57557220433213ee 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -193,7 +193,7 @@
 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
-0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
+0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
index eefd8c6e761d93124f28d548cf932f80a3eaa277..f11c06259d12d694846b3c9ebcb61d295d415470 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -1,6 +1,5 @@
 # RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
-0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
@@ -129,6 +128,7 @@
 0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
 0x00 0x00 0x1b 0xd8 # CHECK: jrc $27
 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
+0x19 0x00 0x80 0xec # CHECK: lapc $4, 100
 0x43 0x0d 0xc8 0x49 # CHECK: ldc2 $8, -701($1)
 0x48 0x3c 0x58 0xec # CHECK: ldpc $2, 123456
 0xb6 0xb3 0x42 0x7e # CHECK: ll $2, -153($18)

diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 89c49e28dc67ad575546b5737d4e58583a140317..c28ff7d719d1d0b70f19f6c1411bceff12900cf7 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -218,7 +218,7 @@
 0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456
 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
-0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
+0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
 0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

diff --git a/test/MC/Mips/micromips32r6/invalid.s b/test/MC/Mips/micromips32r6/invalid.s
index 35ea212578fa6084b9d04706624a7ed72226836a..22ec6395cbad658061f774247ebf27b66249eb37 100644 (file)
--- a/test/MC/Mips/micromips32r6/invalid.s
+++ b/test/MC/Mips/micromips32r6/invalid.s
@@ -38,6 +38,10 @@
                            # FIXME: This ought to point at the $34 but memory is treated as one operand.
   swe $5, 8($34)           # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
   swe $5, 512($4)          # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
+  lapc $7, 1048576         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+  lapc $6, -1048580        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+  lapc $3, 3               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+  lapc $3, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
   lbu16 $9, 8($16)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   lbu16 $3, -2($16)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   lbu16 $3, -2($16)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range

diff --git a/test/MC/Mips/micromips32r6/relocations.s b/test/MC/Mips/micromips32r6/relocations.s
index 959cdbfeac946938e698051693330122f8a442dc..7e8f3f6107e6a5fbc0fad1214934656900303685 100644 (file)
--- a/test/MC/Mips/micromips32r6/relocations.s
+++ b/test/MC/Mips/micromips32r6/relocations.s
@@ -11,7 +11,10 @@
 # CHECK-FIXUP: bc    bar        # encoding: [0b100101AA,A,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar-4, kind: fixup_MICROMIPS_PC26_S1
-# CHECK-FIXUP: addiupc $2, bar  # encoding: [0x78,0b01000AAA,A,A]
+# CHECK-FIXUP: lapc  $2, bar    # encoding: [0x78,0b01000AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
+# CHECK-FIXUP: lapc  $2, bar    # encoding: [0x78,0b01000AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
 # CHECK-FIXUP: lwpc    $2, bar  # encoding: [0x78,0b01001AAA,A,A]
@@ -31,13 +34,15 @@
 # CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
 # CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
-# CHECK-ELF:     0x10 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x10 R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0x14 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x18 R_MICROMIPS_PC21_S1 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
   bc    bar
   addiupc $2,bar
+  lapc    $2,bar
   lwpc    $2,bar
   beqzc  $3, bar
   bnezc  $3, bar

diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s
index a5a55d741a7dede38ef4974d333a8059e009591b..66fcf72ec7fb5e094c28da0c0db02303d1e68545 100644 (file)
--- a/test/MC/Mips/micromips32r6/valid.s
+++ b/test/MC/Mips/micromips32r6/valid.s
@@ -4,7 +4,7 @@
   add $3, $4, $5           # CHECK: add $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x10]
   addiu $3, $4, 1234       # CHECK: addiu $3, $4, 1234  # encoding: [0x30,0x64,0x04,0xd2]
   addu $3, $4, $5          # CHECK: addu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0x50]
-  addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0x78,0x80,0x00,0x19]
+  addiupc $4, 100          # CHECK: lapc $4, 100        # encoding: [0x78,0x80,0x00,0x19]
   addiur1sp $7, 4          # CHECK: addiur1sp $7, 4     # encoding: [0x6f,0x83]
   addiur2 $6, $7, -1       # CHECK: addiur2 $6, $7, -1  # encoding: [0x6f,0x7e]
   addiur2 $6, $7, 12       # CHECK: addiur2 $6, $7, 12  # encoding: [0x6f,0x76]
@@ -63,6 +63,9 @@
   jic   $5, 256            # CHECK: jic $5, 256         # encoding: [0xa0,0x05,0x01,0x00]
   jrc16 $9                 # CHECK: jrc16 $9            # encoding: [0x45,0x23]
   jrcaddiusp 20            # CHECK: jrcaddiusp 20       # encoding: [0x44,0xb3]
+  lapc $4, 100             # CHECK: lapc $4, 100        # encoding: [0x78,0x80,0x00,0x19]
+  lapc $7, 1048572         # CHECK: lapc $7, 1048572    # encoding: [0x78,0xe3,0xff,0xff]
+  lapc $7, -1048576        # CHECK: lapc $7, -1048576   # encoding: [0x78,0xe4,0x00,0x00]
   lh $2, 8($4)             # CHECK: lh $2, 8($4)        # encoding: [0x3c,0x44,0x00,0x08]
   lhe $4, 8($2)            # CHECK: lhe $4, 8($2)       # encoding: [0x60,0x82,0x6a,0x08]
   lhu $4, 8($2)            # CHECK: lhu $4, 8($2)       # encoding: [0x34,0x82,0x00,0x08]

diff --git a/test/MC/Mips/micromips64r6/relocations.s b/test/MC/Mips/micromips64r6/relocations.s
index 18fa26b4e94f2d8b2e88a25ecfceba0eaae5da50..8f871def1805d3593b8fc3fbf57b36aa2737a6d8 100644 (file)
--- a/test/MC/Mips/micromips64r6/relocations.s
+++ b/test/MC/Mips/micromips64r6/relocations.s
@@ -11,7 +11,10 @@
 # CHECK-FIXUP: bc    bar        # encoding: [0b100101AA,A,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar-4, kind: fixup_MICROMIPS_PC26_S1
-# CHECK-FIXUP: addiupc $2, bar  # encoding: [0x78,0b01000AAA,A,A]
+# CHECK-FIXUP: lapc  $2, bar    # encoding: [0x78,0b01000AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
+# CHECK-FIXUP: lapc  $2, bar    # encoding: [0x78,0b01000AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
 # CHECK-FIXUP: lwpc    $2,  bar # encoding: [0x78,0b01001AAA,A,A]
@@ -34,14 +37,16 @@
 # CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
 # CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
-# CHECK-ELF:     0x10 R_MICROMIPS_PC18_S3 bar 0x0
-# CHECK-ELF:     0x14 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x10 R_MICROMIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x14 R_MICROMIPS_PC18_S3 bar 0x0
 # CHECK-ELF:     0x18 R_MICROMIPS_PC21_S1 bar 0x0
+# CHECK-ELF:     0x1C R_MICROMIPS_PC21_S1 bar 0x0
 # CHECK-ELF: ]
 
   balc  bar
   bc    bar
   addiupc $2,bar
+  lapc    $2,bar
   lwpc    $2,bar
   ldpc  $2, bar
   beqzc  $3, bar

diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s
index 4dde2c340570e0700422bd417e6bec51b54ad5b8..fac106fc949a2d13042382d46b863d350e85830a 100644 (file)
--- a/test/MC/Mips/mips32r6/invalid.s
+++ b/test/MC/Mips/mips32r6/invalid.s
@@ -123,6 +123,10 @@ local_label:
         evp 3                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         jalr.hb $31          # CHECK: :[[@LINE]]:9: error: source and destination must be different
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:9: error: source and destination must be different
+        lapc $7, 1048576     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+        lapc $6, -1048580    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+        lapc $3, 3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+        lapc $3, -1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
         ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         ldc2 $20, 1024($s2)  # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
         lsa $2, $3, $4, 0    # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4

diff --git a/test/MC/Mips/mips32r6/relocations.s b/test/MC/Mips/mips32r6/relocations.s
index 3c572896249144fc57e1e36c9315af203a828f6d..c72fcb749efe58cc32e6b0253439a8e1954eaa22 100644 (file)
--- a/test/MC/Mips/mips32r6/relocations.s
+++ b/test/MC/Mips/mips32r6/relocations.s
@@ -5,7 +5,7 @@
 #------------------------------------------------------------------------------
 # Check that the assembler can handle the documented syntax for fixups.
 #------------------------------------------------------------------------------
-# CHECK-FIXUP: addiupc $2, bar  # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP: lapc $2, bar     # encoding: [0xec,0b01000AAA,A,A]
 # CHECK-FIXUP:                  # fixup A - offset: 0,
 # CHECK-FIXUP:                    value: bar, kind: fixup_MIPS_PC19_S2
 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
@@ -34,6 +34,9 @@
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: %pcrel_lo(bar),
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: lapc $2, bar     # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP:                  # fixup A - offset: 0,
+# CHECK-FIXUP:                    value: bar, kind: fixup_MIPS_PC19_S2
 # CHECK-FIXUP: lwpc    $2, bar  # encoding: [0xec,0b01001AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
@@ -55,6 +58,7 @@
 # CHECK-ELF:     0x20 R_MIPS_PCLO16 bar 0x0
 # CHECK-ELF:     0x24 R_MIPS_PC19_S2 bar 0x0
 # CHECK-ELF:     0x28 R_MIPS_PC19_S2 bar 0x0
+# CHECK-ELF:     0x2C R_MIPS_PC19_S2 bar 0x0
 # CHECK-ELF: ]
 
   addiupc   $2,bar
@@ -66,5 +70,6 @@
   bc    bar
   aluipc $2, %pcrel_hi(bar)
   addiu  $2, $2, %pcrel_lo(bar)
+  lapc      $2,bar
   lwpc      $2,bar
   lwupc     $2,bar

diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s
index f9fc16d4a2654c8e59f3af28893a03ddefff906c..498c42f9b37d69b08114064ecbe5138ef08cd9e7 100644 (file)
--- a/test/MC/Mips/mips32r6/valid.s
+++ b/test/MC/Mips/mips32r6/valid.s
@@ -16,7 +16,7 @@ a:
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
         and     $2,4             # CHECK: andi $2, $2, 4      # encoding: [0x30,0x42,0x00,0x04]
-        addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0xec,0x80,0x00,0x19]
+        addiupc $4, 100          # CHECK: lapc $4, 100        # encoding: [0xec,0x80,0x00,0x19]
         addu    $9,10            # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         align   $4, $2, $3, 2    # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
         aluipc  $3, 56           # CHECK: aluipc $3, 56       # encoding: [0xec,0x7f,0x00,0x38]
@@ -113,6 +113,7 @@ a:
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
         l.s     $f2, 8($3)       # CHECK: lwc1 $f2, 8($3)  # encoding: [0xc4,0x62,0x00,0x08]
         l.d     $f2, 8($3)       # CHECK: ldc1 $f2, 8($3)  # encoding: [0xd4,0x62,0x00,0x08]
+        lapc    $4, 100          # CHECK: lapc $4, 100     # encoding: [0xec,0x80,0x00,0x19]
         lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
         lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
         lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]

diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s
index 954decb2f10fbb13c759056285fa311ecf9b2eae..076e2fd7d2b5708416d6547f60b48c780f292e20 100644 (file)
--- a/test/MC/Mips/mips64r6/invalid.s
+++ b/test/MC/Mips/mips64r6/invalid.s
@@ -137,6 +137,10 @@ local_label:
         evp 3                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         jalr.hb $31          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+        lapc $7, 1048576     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+        lapc $6, -1048580    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+        lapc $3, 3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
+        lapc $3, -1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 19-bit signed immediate and multiple of 4
         lsa     $2, $3, $4, 0     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         lsa     $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         pref -1, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate

diff --git a/test/MC/Mips/mips64r6/relocations.s b/test/MC/Mips/mips64r6/relocations.s
index d5a65cd947318a9284bd206c3c68481db63ce12d..4f4efda07c6953780e9c96eb4317c08444baa6c0 100644 (file)
--- a/test/MC/Mips/mips64r6/relocations.s
+++ b/test/MC/Mips/mips64r6/relocations.s
@@ -5,7 +5,7 @@
 #------------------------------------------------------------------------------
 # Check that the assembler can handle the documented syntax for fixups.
 #------------------------------------------------------------------------------
-# CHECK-FIXUP: addiupc $2, bar  # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP: lapc    $2, bar  # encoding: [0xec,0b01000AAA,A,A]
 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
 # CHECK-FIXUP: beqc     $5, $6, bar # encoding: [0x20,0xa6,A,A]
@@ -34,6 +34,9 @@
 # CHECK-FIXUP:                              #   fixup A - offset: 0,
 # CHECK-FIXUP:                                  value: %pcrel_lo(bar),
 # CHECK-FIXUP:                                  kind: fixup_MIPS_PCLO16
+# CHECK-FIXUP: lapc    $2, bar  # encoding: [0xec,0b01000AAA,A,A]
+# CHECK-FIXUP:                  #   fixup A - offset: 0,
+# CHECK-FIXUP:                      value: bar, kind: fixup_MIPS_PC19_S2
 # CHECK-FIXUP: ldpc    $2, bar  # encoding: [0xec,0b010110AA,A,A]
 # CHECK-FIXUP:                  # fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar,
@@ -57,9 +60,10 @@
 # CHECK-ELF:     0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
 # CHECK-ELF:     0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
 # CHECK-ELF:     0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x24 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x28 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x24 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x28 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
 # CHECK-ELF:     0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x30 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
 # CHECK-ELF: ]
 
   addiupc   $2,bar
@@ -71,6 +75,7 @@
   bc    bar
   aluipc $2, %pcrel_hi(bar)
   addiu  $2, $2, %pcrel_lo(bar)
+  lapc  $2,bar
   ldpc  $2,bar
   lwpc  $2,bar
   lwupc $2,bar

diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s
index 486738baa84d75f3ef2b791e4fbe5d5c36f071e6..e04725c2329657405a24f918abe1875d17fec872 100644 (file)
--- a/test/MC/Mips/mips64r6/valid.s
+++ b/test/MC/Mips/mips64r6/valid.s
@@ -15,7 +15,7 @@
 a:
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
-        addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0xec,0x80,0x00,0x19]
+        addiupc $4, 100          # CHECK: lapc $4, 100        # encoding: [0xec,0x80,0x00,0x19]
         addu    $9,10            # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         align   $4, $2, $3, 2    # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
         aluipc  $3, 56           # CHECK: aluipc $3, 56       # encoding: [0xec,0x7f,0x00,0x38]
@@ -158,6 +158,7 @@ a:
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
         l.s     $f2, 8($3)       # CHECK: lwc1  $f2, 8($3)       # encoding: [0xc4,0x62,0x00,0x08]
         l.d     $f2, 8($3)       # CHECK: ldc1  $f2, 8($3)       # encoding: [0xd4,0x62,0x00,0x08]
+        lapc    $4, 100          # CHECK: lapc $4, 100           # encoding: [0xec,0x80,0x00,0x19]
         ldc2    $8, -701($at)    # CHECK: ldc2 $8, -701($1)      # encoding: [0x49,0xc8,0x0d,0x43]
         ldpc    $2,123456        # CHECK: ldpc $2, 123456  # encoding: [0xec,0x58,0x3c,0x48]
         ll      $v0,-153($s2)    # CHECK: ll $2, -153($18)       # encoding: [0x7e,0x42,0xb3,0xb6]