]> granicus.if.org Git - llvm/commitdiff
[UnreachableBlockElim] Check return value of constrainRegClass().
authorMikael Holmen <mikael.holmen@ericsson.com>
Wed, 10 May 2017 06:33:43 +0000 (06:33 +0000)
committerMikael Holmen <mikael.holmen@ericsson.com>
Wed, 10 May 2017 06:33:43 +0000 (06:33 +0000)
Summary:
MachineRegisterInfo::constrainRegClass() can fail if two register classes
don't have a common subclass or if the register class doesn't contain
enough registers. Check the return value before trying to remove Phi nodes,
and if we can't constrain, we output a COPY instead of simply replacing
registers.

Reviewers: kparzysz, david2050, wmi

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302622 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/UnreachableBlockElim.cpp

index f085132b6a94a8eef5986a4a84b0a32a45f021d1..407fd9b162e975a0b646e347a7b03b811a88f713 100644 (file)
@@ -206,11 +206,12 @@ bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) {
         if (InputReg != OutputReg) {
           MachineRegisterInfo &MRI = F.getRegInfo();
           unsigned InputSub = Input.getSubReg();
-          if (InputSub == 0) {
-            MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg));
+          if (InputSub == 0 &&
+              MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg))) {
             MRI.replaceRegWith(OutputReg, InputReg);
           } else {
-            // The input register to the PHI has a subregister:
+            // The input register to the PHI has a subregister or it can't be
+            // constrained to the proper register class:
             // insert a COPY instead of simply replacing the output
             // with the input.
             const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo();