* yasm_arch.xml, yasm_arch.7: Fix typo in 64-bit implicit zero extension

example code.

Noticed by: mu@

svn path=/trunk/yasm/; revision=1145

diff --git a/modules/arch/yasm_arch.7 b/modules/arch/yasm_arch.7
index b1c36d0f057f27b1db5507fdf7698eb91ecc1ee1..24eae9de25405771d9310e7e74d00a49ba7a93f3 100644 (file)
--- a/modules/arch/yasm_arch.7
+++ b/modules/arch/yasm_arch.7
@@ -90,7 +90,7 @@ Results of 32\-bit operations are implicitly zero\-extended to the upper 32 bits
 .IP
 mov ecx, 1  ; 1 byte shorter than mov rcx, 1
 .IP
-and edx, 3  ; equivalent to and rdx, 5
+and edx, 3  ; equivalent to and rdx, 3
 .PP
 For most instructions in 64\-bit mode, immediate values remain 32 bits; their value is sign\-extended into the upper 32 bits of the target register prior to being used\&. The exception is the mov instruction, which can take a 64\-bit immediate when the destination is a 64\-bit register\&. Examples in NASM syntax:
 

diff --git a/modules/arch/yasm_arch.xml b/modules/arch/yasm_arch.xml
index dacf2cc1cc3d30809262ee635530f6716cba30dd..4b0cc0fdf0c5903634ebc8f19f27c1de32552956 100644 (file)
--- a/modules/arch/yasm_arch.xml
+++ b/modules/arch/yasm_arch.xml
@@ -169,7 +169,7 @@
                 Examples in NASM syntax:</para>
 
             <screen>mov ecx, 1  ; 1 byte shorter than mov rcx, 1</screen>
-            <screen>and edx, 3  ; equivalent to and rdx, 5</screen>
+            <screen>and edx, 3  ; equivalent to and rdx, 3</screen>
 
         </refsect3>