Add Intel SHA instructions.

Contributed by: Mark Charney @ Intel

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index ceed1840eee39209d73f3a5c0e9f46886777736c..c4aedf04c995236864f69c30c6cbbe686e1a0444 100755 (executable)
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -39,7 +39,7 @@ ordered_cpu_features = [
     "SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
     "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "F16C",
     "FSGSBASE", "RDRAND", "XSAVEOPT", "EPTVPID", "SMX", "AVX2", "BMI1",
-    "BMI2", "INVPCID", "LZCNT", "TBM", "TSX"]
+    "BMI2", "INVPCID", "LZCNT", "TBM", "TSX", "SHA"]
 unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
 
 # Predefined VEX prefix field values
@@ -8056,6 +8056,55 @@ add_group("invpcid",
               Operand(type="Mem", size=128, relaxed=True, dest="EA")])
 add_insn("invpcid", "invpcid")
 
+
+#####################################################################
+add_group("intel_SHA1MSG1",
+       cpu=["SHA"],
+       opcode=[0x0F, 0x38, 0xC9],
+       operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+               Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA1MSG2",
+       cpu=["SHA"],
+       opcode=[0x0F, 0x38, 0xCA],
+       operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+               Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA1NEXTE",
+       cpu=["SHA"],
+       opcode=[0x0F, 0x38, 0xC8],
+       operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+               Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA1RNDS4",
+       cpu=["SHA"],
+       opcode=[0x0F, 0x3A, 0xCC],
+       operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+               Operand(type="SIMDRM", size=128, dest="EA", relaxed=True),
+               Operand(type="Imm", size=8, dest="Imm", relaxed=True)])
+add_group("intel_SHA256MSG1",
+       cpu=["SHA"],
+       opcode=[0x0F, 0x38, 0xCC],
+       operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+               Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA256MSG2",
+       cpu=["SHA"],
+       opcode=[0x0F, 0x38, 0xCD],
+       operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+               Operand(type="SIMDRM", size=128, dest="EA", relaxed=True)])
+add_group("intel_SHA256RNDS2",
+       cpu=["SHA"],
+       opcode=[0x0F, 0x38, 0xCB],
+       operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
+               Operand(type="SIMDReg", size=128, dest="EA")])
+
+
+add_insn("SHA1MSG1", "intel_SHA1MSG1")
+add_insn("SHA1MSG2", "intel_SHA1MSG2")
+add_insn("SHA1NEXTE", "intel_SHA1NEXTE")
+add_insn("SHA1RNDS4", "intel_SHA1RNDS4")
+add_insn("SHA256MSG1", "intel_SHA256MSG1")
+add_insn("SHA256MSG2", "intel_SHA256MSG2")
+add_insn("SHA256RNDS2", "intel_SHA256RNDS2")
+
+
 #####################################################################
 # AMD trailing bit manipulation (TBM)
 #####################################################################

diff --git a/modules/arch/x86/x86arch.h b/modules/arch/x86/x86arch.h
index 14b2b2e363f2d015c5704567c6f3c07c9c3dad78..7ad104667f51f05187fe40e718121ee57553b260 100644 (file)
--- a/modules/arch/x86/x86arch.h
+++ b/modules/arch/x86/x86arch.h
@@ -85,6 +85,7 @@
 #define CPU_LZCNT   51      /* Intel LZCNT instruction */
 #define CPU_TBM     52      /* AMD TBM instruction */
 #define CPU_TSX     53      /* Intel TSX instructions */
+#define CPU_SHA     54      /* Intel SHA instructions */
 
 enum x86_parser_type {
     X86_PARSER_NASM = 0,

diff --git a/modules/arch/x86/x86cpu.gperf b/modules/arch/x86/x86cpu.gperf
index 3d49574646d9e9c468fadca193aa7ec8b3d0cdd3..d680866083ff3458d1f095b8dac9a8cb8c968b02 100644 (file)
--- a/modules/arch/x86/x86cpu.gperf
+++ b/modules/arch/x86/x86cpu.gperf
@@ -402,6 +402,8 @@ lzcnt,              x86_cpu_set,    CPU_LZCNT
 nolzcnt,       x86_cpu_clear,  CPU_LZCNT
 tbm,           x86_cpu_set,    CPU_TBM
 notbm, x86_cpu_clear,  CPU_TBM
+sha,           x86_cpu_set,    CPU_SHA
+nosha,         x86_cpu_clear,  CPU_SHA
 # Change NOP patterns
 basicnop,      x86_nop,        X86_NOP_BASIC
 intelnop,      x86_nop,        X86_NOP_INTEL