[LVI][CVP] Add support for abs/nabs select pattern flavor

Based on ConstantRange support added in D61084, we can now handle
abs and nabs select pattern flavors in LVI.

Differential Revision: https://reviews.llvm.org/D61794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360700 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Analysis/LazyValueInfo.cpp b/lib/Analysis/LazyValueInfo.cpp
index e7ca69150c06b89bd6c500eec0628c8180b64a48..4f6a344170122d88f9edcd1645c13f4befef0384 100644 (file)
--- a/lib/Analysis/LazyValueInfo.cpp
+++ b/lib/Analysis/LazyValueInfo.cpp
@@ -893,7 +893,28 @@ bool LazyValueInfoImpl::solveBlockValueSelect(ValueLatticeElement &BBLV,
       return true;
     }
 
-    // TODO: ABS, NABS from the SelectPatternResult
+    if (SPR.Flavor == SPF_ABS) {
+      if (LHS == SI->getTrueValue()) {
+        BBLV = ValueLatticeElement::getRange(TrueCR.abs());
+        return true;
+      }
+      if (LHS == SI->getFalseValue()) {
+        BBLV = ValueLatticeElement::getRange(FalseCR.abs());
+        return true;
+      }
+    }
+
+    if (SPR.Flavor == SPF_NABS) {
+      ConstantRange Zero(APInt::getNullValue(TrueCR.getBitWidth()));
+      if (LHS == SI->getTrueValue()) {
+        BBLV = ValueLatticeElement::getRange(Zero.sub(TrueCR.abs()));
+        return true;
+      }
+      if (LHS == SI->getFalseValue()) {
+        BBLV = ValueLatticeElement::getRange(Zero.sub(FalseCR.abs()));
+        return true;
+      }
+    }
   }
 
   // Can we constrain the facts about the true and false values by using the

diff --git a/test/Transforms/CorrelatedValuePropagation/basic.ll b/test/Transforms/CorrelatedValuePropagation/basic.ll
index cd9dff6bb2ff045af0a74851797dbeb2e1ed9568..b768ebd85acc922d2a77baf215ee0accb09dd4c9 100644 (file)
--- a/test/Transforms/CorrelatedValuePropagation/basic.ll
+++ b/test/Transforms/CorrelatedValuePropagation/basic.ll
@@ -633,8 +633,7 @@ define void @abs1(i32 %a, i1* %p) {
 ; CHECK-NEXT:    store i1 true, i1* [[P:%.*]]
 ; CHECK-NEXT:    [[C2:%.*]] = icmp slt i32 [[ABS]], 19
 ; CHECK-NEXT:    store i1 [[C2]], i1* [[P]]
-; CHECK-NEXT:    [[C3:%.*]] = icmp sge i32 [[ABS]], 0
-; CHECK-NEXT:    store i1 [[C3]], i1* [[P]]
+; CHECK-NEXT:    store i1 true, i1* [[P]]
 ; CHECK-NEXT:    [[C4:%.*]] = icmp sge i32 [[ABS]], 1
 ; CHECK-NEXT:    store i1 [[C4]], i1* [[P]]
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -684,8 +683,7 @@ define void @abs2(i32 %a, i1* %p) {
 ; CHECK-NEXT:    store i1 true, i1* [[P:%.*]]
 ; CHECK-NEXT:    [[C2:%.*]] = icmp slt i32 [[ABS]], 19
 ; CHECK-NEXT:    store i1 [[C2]], i1* [[P]]
-; CHECK-NEXT:    [[C3:%.*]] = icmp sge i32 [[ABS]], 0
-; CHECK-NEXT:    store i1 [[C3]], i1* [[P]]
+; CHECK-NEXT:    store i1 true, i1* [[P]]
 ; CHECK-NEXT:    [[C4:%.*]] = icmp sge i32 [[ABS]], 1
 ; CHECK-NEXT:    store i1 [[C4]], i1* [[P]]
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -735,8 +733,7 @@ define void @nabs1(i32 %a, i1* %p) {
 ; CHECK-NEXT:    store i1 true, i1* [[P:%.*]]
 ; CHECK-NEXT:    [[C2:%.*]] = icmp sgt i32 [[NABS]], -19
 ; CHECK-NEXT:    store i1 [[C2]], i1* [[P]]
-; CHECK-NEXT:    [[C3:%.*]] = icmp sle i32 [[NABS]], 0
-; CHECK-NEXT:    store i1 [[C3]], i1* [[P]]
+; CHECK-NEXT:    store i1 true, i1* [[P]]
 ; CHECK-NEXT:    [[C4:%.*]] = icmp sle i32 [[NABS]], -1
 ; CHECK-NEXT:    store i1 [[C4]], i1* [[P]]
 ; CHECK-NEXT:    br label [[EXIT]]
@@ -786,8 +783,7 @@ define void @nabs2(i32 %a, i1* %p) {
 ; CHECK-NEXT:    store i1 true, i1* [[P:%.*]]
 ; CHECK-NEXT:    [[C2:%.*]] = icmp sgt i32 [[NABS]], -19
 ; CHECK-NEXT:    store i1 [[C2]], i1* [[P]]
-; CHECK-NEXT:    [[C3:%.*]] = icmp sle i32 [[NABS]], 0
-; CHECK-NEXT:    store i1 [[C3]], i1* [[P]]
+; CHECK-NEXT:    store i1 true, i1* [[P]]
 ; CHECK-NEXT:    [[C4:%.*]] = icmp sle i32 [[NABS]], -1
 ; CHECK-NEXT:    store i1 [[C4]], i1* [[P]]
 ; CHECK-NEXT:    br label [[EXIT]]