[SystemZ] Make better use of VGEF/VGEG

Current code in SystemZDAGToDAGISel::tryGather refuses to perform
any transformation if the Load SDNode has more than one use.  This
(erronously) counts uses of the chain result, which prevents the
optimization in many cases unnecessarily.  Fixed by this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349748 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 0d2c2389847f6b643f1cfa5ee22a8ab89020e7fa..4fbb59ea0df9efbf432ffbefd9c507f1a00d5d6b 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -1147,7 +1147,7 @@ bool SystemZDAGToDAGISel::tryGather(SDNode *N, unsigned Opcode) {
     return false;
 
   auto *Load = dyn_cast<LoadSDNode>(N->getOperand(1));
-  if (!Load || !Load->hasOneUse())
+  if (!Load || !Load->hasNUsesOfValue(1, 0))
     return false;
   if (Load->getMemoryVT().getSizeInBits() !=
       Load->getValueType(0).getSizeInBits())

diff --git a/test/CodeGen/SystemZ/vec-move-08.ll b/test/CodeGen/SystemZ/vec-move-08.ll
index 5396a1edec6abc0384d1baf0effbd110ee664f22..7c4a16c95403d344be6c9b97ecbc115e96a8c4a4 100644 (file)
--- a/test/CodeGen/SystemZ/vec-move-08.ll
+++ b/test/CodeGen/SystemZ/vec-move-08.ll
@@ -442,3 +442,35 @@ define <2 x double> @f39(<2 x double> %val, <2 x i64> %index, i64 %base) {
   %ret = insertelement <2 x double> %val, double %element, i32 1
   ret <2 x double> %ret
 }
+
+; Test a v4i32 gather where the load is chained.
+define void @f40(<4 x i32> %val, <4 x i32> %index, i64 %base, <4 x i32> *%res) {
+; CHECK-LABEL: f40:
+; CHECK: vgef %v24, 0(%v26,%r2), 1
+; CHECK: vst %v24, 0(%r3)
+; CHECK: br %r14
+  %elem = extractelement <4 x i32> %index, i32 1
+  %ext = zext i32 %elem to i64
+  %add = add i64 %base, %ext
+  %ptr = inttoptr i64 %add to i32 *
+  %element = load i32, i32 *%ptr
+  %ret = insertelement <4 x i32> %val, i32 %element, i32 1
+  store <4 x i32> %ret, <4 x i32> *%res
+  ret void
+}
+
+; Test a v2i64 gather where the load is chained.
+define void @f41(<2 x i64> %val, <2 x i64> %index, i64 %base, <2 x i64> *%res) {
+; CHECK-LABEL: f41:
+; CHECK: vgeg %v24, 0(%v26,%r2), 1
+; CHECK: vst %v24, 0(%r3)
+; CHECK: br %r14
+  %elem = extractelement <2 x i64> %index, i32 1
+  %add = add i64 %base, %elem
+  %ptr = inttoptr i64 %add to i64 *
+  %element = load i64, i64 *%ptr
+  %ret = insertelement <2 x i64> %val, i64 %element, i32 1
+  store <2 x i64> %ret, <2 x i64> *%res
+  ret void
+}
+