[SystemZ] Correct the SchedModel regarding vector unit / instructions.

* Use a generic vector unit to model the issue unit more accurately.
* Update some vector instructions that actually use the vector unit for more
  than one cycle.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286112 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZSchedule.td b/lib/Target/SystemZ/SystemZSchedule.td
index 2a8c73a4e6b3f48195cee4ba00825e1fcea172d7..dbba8ab42b5a54679e59f8b5e5259df67bfdc91a 100644 (file)
--- a/lib/Target/SystemZ/SystemZSchedule.td
+++ b/lib/Target/SystemZ/SystemZSchedule.td
@@ -8,6 +8,9 @@
 //===----------------------------------------------------------------------===//
 
 // Scheduler resources
+// Resources ending with a '2' use that resource for 2 cycles. An instruction
+// using two such resources use the mapped unit for 4 cycles, and 2 is added
+// to the total number of uops of the sched class.
 
 // These three resources are used to express decoder grouping rules.
 // The number of decoder slots needed by an instructions is normally
@@ -38,6 +41,7 @@ def Lat30 : SchedWrite;
 
 // Fixed-point
 def FXa         : SchedWrite;
+def FXa2        : SchedWrite;
 def FXb         : SchedWrite;
 def FXU         : SchedWrite;
 
@@ -50,11 +54,14 @@ def LSU         : SchedWrite;
 def LSU_lat1    : SchedWrite;
 
 // Floating point unit (zEC12 and earlier)
-def FPU : SchedWrite;
+def FPU  : SchedWrite;
+def FPU2 : SchedWrite;
 
 // Vector sub units (z13)
 def VecBF     : SchedWrite;
+def VecBF2    : SchedWrite;
 def VecDF     : SchedWrite;
+def VecDF2    : SchedWrite;
 def VecFPd    : SchedWrite; // Blocking BFP div/sqrt unit.
 def VecMul    : SchedWrite;
 def VecStr    : SchedWrite;

diff --git a/lib/Target/SystemZ/SystemZScheduleZ13.td b/lib/Target/SystemZ/SystemZScheduleZ13.td
index 815a41f5411196d80199a501c98c92882278c04a..211fbdececf38e4256dd34aa1c6f54720452541c 100644 (file)
--- a/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -63,20 +63,19 @@ def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
 def Z13_FXaUnit     : ProcResource<2>;
 def Z13_FXbUnit     : ProcResource<2>;
 def Z13_LSUnit      : ProcResource<2>;
-def Z13_VecBFUnit   : ProcResource<2>;
-def Z13_VecDFUnit   : ProcResource<2>;
+def Z13_VecUnit     : ProcResource<2>;
 def Z13_VecFPdUnit  : ProcResource<2> { let BufferSize = 1; /* blocking */ }
-def Z13_VecMulUnit  : ProcResource<2>;
-def Z13_VecStrUnit  : ProcResource<2>;
-def Z13_VecXsPmUnit : ProcResource<2>;
 def Z13_VBUnit      : ProcResource<2>;
 
 // Subtarget specific definitions of scheduling resources.
-def : WriteRes<FXa,     [Z13_FXaUnit]>   { let Latency = 1; }
-def : WriteRes<FXb,     [Z13_FXbUnit]>   { let Latency = 1; }
-def : WriteRes<LSU,     [Z13_LSUnit]>    { let Latency = 4; }
-def : WriteRes<VecBF,   [Z13_VecBFUnit]> { let Latency = 8; }
-def : WriteRes<VecDF,   [Z13_VecDFUnit]>;
+def : WriteRes<FXa,     [Z13_FXaUnit]> { let Latency = 1; }
+def : WriteRes<FXa2,    [Z13_FXaUnit, Z13_FXaUnit]> { let Latency = 2; }
+def : WriteRes<FXb,     [Z13_FXbUnit]> { let Latency = 1; }
+def : WriteRes<LSU,     [Z13_LSUnit]>  { let Latency = 4; }
+def : WriteRes<VecBF,   [Z13_VecUnit]> { let Latency = 8; }
+def : WriteRes<VecBF2,  [Z13_VecUnit, Z13_VecUnit]> { let Latency = 9; }
+def : WriteRes<VecDF,   [Z13_VecUnit]> { let Latency = 8; }
+def : WriteRes<VecDF2,  [Z13_VecUnit, Z13_VecUnit]> { let Latency = 9; }
 def : WriteRes<VecFPd,  [Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
                          Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
                          Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
@@ -88,9 +87,9 @@ def : WriteRes<VecFPd,  [Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
                          Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit,
                          Z13_VecFPdUnit, Z13_VecFPdUnit, Z13_VecFPdUnit]>
                          { let Latency = 30; }
-def : WriteRes<VecMul,  [Z13_VecMulUnit]>  { let Latency = 5; }
-def : WriteRes<VecStr,  [Z13_VecStrUnit]>  { let Latency = 4; }
-def : WriteRes<VecXsPm, [Z13_VecXsPmUnit]> { let Latency = 3; }
+def : WriteRes<VecMul,  [Z13_VecUnit]> { let Latency = 5; }
+def : WriteRes<VecStr,  [Z13_VecUnit]> { let Latency = 4; }
+def : WriteRes<VecXsPm, [Z13_VecUnit]> { let Latency = 3; }
 def : WriteRes<VBU,     [Z13_VBUnit]>; // Virtual Branching Unit
 
 // -------------------------- INSTRUCTIONS ---------------------------------- //
@@ -443,9 +442,9 @@ def : InstRW<[FXa, LSU, Lat9], (instregex "MH(Y)?$")>;
 
 def : InstRW<[FXa, Lat30, GroupAlone], (instregex "DSG(F)?R$")>;
 def : InstRW<[LSU, FXa, Lat30, GroupAlone], (instregex "DSG(F)?$")>;
-def : InstRW<[FXa, FXa, Lat20, GroupAlone], (instregex "DLR$")>;
-def : InstRW<[FXa, FXa, Lat30, GroupAlone], (instregex "DLGR$")>;
-def : InstRW<[FXa, FXa, LSU, Lat30, GroupAlone], (instregex "DL(G)?$")>;
+def : InstRW<[FXa2, FXa2, Lat20, GroupAlone], (instregex "DLR$")>;
+def : InstRW<[FXa2, FXa2, Lat30, GroupAlone], (instregex "DLGR$")>;
+def : InstRW<[FXa2, FXa2, LSU, Lat30, GroupAlone], (instregex "DL(G)?$")>;
 
 //===----------------------------------------------------------------------===//
 // Shifts
@@ -644,8 +643,8 @@ def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "LXR$")>;
 def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)BR$")>;
 def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare(_VecPseudo)?$")>;
 def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare(_VecPseudo)?$")>;
-def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "LTXBR$")>;
-def : InstRW<[VecDF, VecDF, Lat11, GroupAlone],
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBR$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone],
              (instregex "LTXBRCompare(_VecPseudo)?$")>;
 
 // Copy sign
@@ -680,16 +679,16 @@ def : InstRW<[VecDF, VecDF, Lat20], (instregex "LDXBR(A)?$")>;
 // Load lengthened
 def : InstRW<[VecBF, LSU, Lat12], (instregex "LDEB$")>;
 def : InstRW<[VecBF], (instregex "LDEBR$")>;
-def : InstRW<[VecBF, VecBF, LSU, Lat12 , GroupAlone], (instregex "LX(D|E)B$")>;
-def : InstRW<[VecBF, VecBF, Lat9 , GroupAlone], (instregex "LX(D|E)BR$")>;
+def : InstRW<[VecBF2, VecBF2, LSU, Lat12 , GroupAlone], (instregex "LX(D|E)B$")>;
+def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "LX(D|E)BR$")>;
 
 // Convert from fixed / logical
 def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CE(F|G)BR$")>;
 def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CD(F|G)BR$")>;
-def : InstRW<[FXb, VecDF, VecDF, Lat12, GroupAlone], (instregex "CX(F|G)BR$")>;
+def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CX(F|G)BR$")>;
 def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CEL(F|G)BR$")>;
 def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CDL(F|G)BR$")>;
-def : InstRW<[FXb, VecDF, VecDF, Lat12, GroupAlone], (instregex "CXL(F|G)BR$")>;
+def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CXL(F|G)BR$")>;
 
 // Convert to fixed / logical
 def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CF(E|D)BR$")>;
@@ -710,7 +709,7 @@ def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)EBR$")>;
 def : InstRW<[FXb], (instregex "LCDFR(_32)?$")>;
 def : InstRW<[FXb], (instregex "LNDFR(_32)?$")>;
 def : InstRW<[FXb], (instregex "LPDFR(_32)?$")>;
-def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "L(C|N|P)XBR$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "L(C|N|P)XBR$")>;
 
 // Square root
 def : InstRW<[VecFPd, LSU], (instregex "SQ(E|D)B$")>;
@@ -720,7 +719,7 @@ def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "SQXBR$")>;
 // Load FP integer
 def : InstRW<[VecBF], (instregex "FIEBR(A)?$")>;
 def : InstRW<[VecBF], (instregex "FIDBR(A)?$")>;
-def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "FIXBR(A)?$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "FIXBR(A)?$")>;
 
 //===----------------------------------------------------------------------===//
 // FP: Binary arithmetic
@@ -729,19 +728,19 @@ def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "FIXBR(A)?$")>;
 // Addition
 def : InstRW<[VecBF, LSU, Lat12], (instregex "A(E|D)B$")>;
 def : InstRW<[VecBF], (instregex "A(E|D)BR$")>;
-def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "AXBR$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "AXBR$")>;
 
 // Subtraction
 def : InstRW<[VecBF, LSU, Lat12], (instregex "S(E|D)B$")>;
 def : InstRW<[VecBF], (instregex "S(E|D)BR$")>;
-def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "SXBR$")>;
+def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "SXBR$")>;
 
 // Multiply
 def : InstRW<[VecBF, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
 def : InstRW<[VecBF], (instregex "M(D|DE|EE)BR$")>;
-def : InstRW<[VecBF, VecBF, LSU, Lat12, GroupAlone], (instregex "MXDB$")>;
-def : InstRW<[VecBF, VecBF, Lat9, GroupAlone], (instregex "MXDBR$")>;
-def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "MXBR$")>;
+def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MXDB$")>;
+def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MXDBR$")>;
+def : InstRW<[VecDF2, VecDF2, Lat20, GroupAlone], (instregex "MXBR$")>;
 
 // Multiply and add / subtract
 def : InstRW<[VecBF, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
@@ -765,7 +764,7 @@ def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "CXBR$")>;
 
 // Test Data Class
 def : InstRW<[LSU, VecXsPm, Lat9], (instregex "TC(E|D)B$")>;
-def : InstRW<[LSU, VecDF, VecDF, Lat15, GroupAlone], (instregex "TCXB$")>;
+def : InstRW<[LSU, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "TCXB$")>;
 
 
 // --------------------------------- Vector --------------------------------- //
@@ -921,26 +920,29 @@ def : InstRW<[VecStr, Lat5], (instregex "VTM$")>;
 // Vector: Floating-point arithmetic
 //===----------------------------------------------------------------------===//
 
-def : InstRW<[VecBF], (instregex "VCD(G|GB|LG|LGB)$")>;
+def : InstRW<[VecBF2], (instregex "VCD(G|GB|LG|LGB)$")>;
 def : InstRW<[VecBF], (instregex "WCD(GB|LGB)$")>;
-def : InstRW<[VecBF], (instregex "VC(L)?GD$")>;
-def : InstRW<[VecBF], (instregex "(V|W)FADB$")>;
-def : InstRW<[VecBF], (instregex "(V|W)CGDB$")>;
-def : InstRW<[VecBF], (instregex "VF(I|M|A|S)$")>;
-def : InstRW<[VecBF], (instregex "VF(I|M|S)DB$")>;
+def : InstRW<[VecBF2], (instregex "VC(L)?GD$")>;
+def : InstRW<[VecBF2], (instregex "VFADB$")>;
+def : InstRW<[VecBF], (instregex "WFADB$")>;
+def : InstRW<[VecBF2], (instregex "VCGDB$")>;
+def : InstRW<[VecBF], (instregex "WCGDB$")>;
+def : InstRW<[VecBF2], (instregex "VF(I|M|A|S)$")>;
+def : InstRW<[VecBF2], (instregex "VF(I|M|S)DB$")>;
 def : InstRW<[VecBF], (instregex "WF(I|M|S)DB$")>;
-def : InstRW<[VecBF], (instregex "(V|W)CLGDB$")>;
+def : InstRW<[VecBF2], (instregex "VCLGDB$")>;
+def : InstRW<[VecBF], (instregex "WCLGDB$")>;
 def : InstRW<[VecXsPm], (instregex "VFL(C|N|P)DB$")>;
 def : InstRW<[VecXsPm], (instregex "WFL(C|N|P)DB$")>;
-def : InstRW<[VecBF], (instregex "VFM(A|S)$")>;
-def : InstRW<[VecBF], (instregex "VFM(A|S)DB$")>;
+def : InstRW<[VecBF2], (instregex "VFM(A|S)$")>;
+def : InstRW<[VecBF2], (instregex "VFM(A|S)DB$")>;
 def : InstRW<[VecBF], (instregex "WFM(A|S)DB$")>;
 def : InstRW<[VecXsPm], (instregex "VFPSO$")>;
 def : InstRW<[VecXsPm], (instregex "(V|W)FPSODB$")>;
 def : InstRW<[VecXsPm, Lat4], (instregex "VFTCI(DB)?$")>;
 def : InstRW<[VecXsPm, Lat4], (instregex "WFTCIDB$")>;
-def : InstRW<[VecBF], (instregex "VL(DE|ED)$")>;
-def : InstRW<[VecBF], (instregex "VL(DE|ED)B$")>;
+def : InstRW<[VecBF2], (instregex "VL(DE|ED)$")>;
+def : InstRW<[VecBF2], (instregex "VL(DE|ED)B$")>;
 def : InstRW<[VecBF], (instregex "WL(DE|ED)B$")>;
 
 // divide / square root

diff --git a/lib/Target/SystemZ/SystemZScheduleZ196.td b/lib/Target/SystemZ/SystemZScheduleZ196.td
index fc478ad7fc79411bafea390693d6c5cbfe8712f4..c61a515f7f610e53be0764fe04791c08850d7065 100644 (file)
--- a/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -65,6 +65,7 @@ def : WriteRes<FXU,       [Z196_FXUnit]> { let Latency = 1; }
 def : WriteRes<LSU,       [Z196_LSUnit]> { let Latency = 4; }
 def : WriteRes<LSU_lat1,  [Z196_LSUnit]> { let Latency = 1; }
 def : WriteRes<FPU,       [Z196_FPUnit]> { let Latency = 8; }
+def : WriteRes<FPU2,      [Z196_FPUnit, Z196_FPUnit]> { let Latency = 9; }
 
 // -------------------------- INSTRUCTIONS ---------------------------------- //
 
@@ -410,13 +411,13 @@ def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
 // Division and remainder
 //===----------------------------------------------------------------------===//
 
-def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DSG(F)?R$")>;
-def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DSG(F)?$")>;
-def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DL(G)?R$")>;
-def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DL(G)?$")>;
 
 //===----------------------------------------------------------------------===//
@@ -589,8 +590,8 @@ def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
-def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "LTXBR$")>;
-def : InstRW<[FPU, FPU, Lat9, GroupAlone],
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
              (instregex "LTXBRCompare(_VecPseudo)?$")>;
 
 // Copy sign
@@ -625,16 +626,16 @@ def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
 // Load lengthened
 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
 def : InstRW<[FPU], (instregex "LDEBR$")>;
-def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
-def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
 
 // Convert from fixed / logical
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR$")>;
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR$")>;
-def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
-def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
 
 // Convert to fixed / logical
 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR$")>;
@@ -654,17 +655,17 @@ def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
-def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
 
 // Square root
 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "SQXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
 
 // Load FP integer
 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
-def : InstRW<[FPU, FPU, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
+def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
 
 //===----------------------------------------------------------------------===//
 // FP: Binary arithmetic
@@ -673,19 +674,19 @@ def : InstRW<[FPU, FPU, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
 // Addition
 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "AXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
 
 // Subtraction
 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "SXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
 
 // Multiply
 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
-def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
-def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "MXDBR$")>;
-def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "MXBR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
 
 // Multiply and add / subtract
 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
@@ -696,7 +697,7 @@ def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
 // Division
 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "DXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
 
 //===----------------------------------------------------------------------===//
 // FP: Comparisons
@@ -709,7 +710,7 @@ def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
 
 // Test Data Class
 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
-def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
 
 }
 

diff --git a/lib/Target/SystemZ/SystemZScheduleZEC12.td b/lib/Target/SystemZ/SystemZScheduleZEC12.td
index 133bb66be2eb4aba417e81a3772f2f3bccc6e97d..9e960dfaee5dd387dbd1ed0a6561da8df9ddfe68 100644 (file)
--- a/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -66,6 +66,7 @@ def : WriteRes<FXU,      [ZEC12_FXUnit]> { let Latency = 1; }
 def : WriteRes<LSU,      [ZEC12_LSUnit]> { let Latency = 4; }
 def : WriteRes<LSU_lat1, [ZEC12_LSUnit]> { let Latency = 1; }
 def : WriteRes<FPU,  [ZEC12_FPUnit]> { let Latency = 8; }
+def : WriteRes<FPU2, [ZEC12_FPUnit, ZEC12_FPUnit]> { let Latency = 9; }
 def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
 
 // -------------------------- INSTRUCTIONS ---------------------------------- //
@@ -414,13 +415,13 @@ def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
 // Division and remainder
 //===----------------------------------------------------------------------===//
 
-def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DSG(F)?R$")>;
-def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DSG(F)?$")>;
-def : InstRW<[FPU, FPU, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DL(G)?R$")>;
-def : InstRW<[FPU, FPU, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
+def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
               (instregex "DL(G)?$")>;
 
 //===----------------------------------------------------------------------===//
@@ -619,8 +620,8 @@ def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
-def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "LTXBR$")>;
-def : InstRW<[FPU, FPU, Lat9, GroupAlone],
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
              (instregex "LTXBRCompare(_VecPseudo)?$")>;
 
 // Copy sign
@@ -655,16 +656,16 @@ def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
 // Load lengthened
 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
 def : InstRW<[FPU], (instregex "LDEBR$")>;
-def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
-def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
 
 // Convert from fixed / logical
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR$")>;
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR$")>;
-def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR$")>;
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
-def : InstRW<[FXU, FPU, FPU, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
+def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
 
 // Convert to fixed / logical
 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR$")>;
@@ -684,17 +685,17 @@ def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
-def : InstRW<[FPU, FPU, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
+def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
 
 // Square root
 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "SQXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
 
 // Load FP integer
 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
-def : InstRW<[FPU, FPU, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
+def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
 
 //===----------------------------------------------------------------------===//
 // FP: Binary arithmetic
@@ -703,19 +704,19 @@ def : InstRW<[FPU, FPU, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
 // Addition
 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "AXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
 
 // Subtraction
 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat20, GroupAlone], (instregex "SXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
 
 // Multiply
 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
-def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
-def : InstRW<[FPU, FPU, Lat10, GroupAlone], (instregex "MXDBR$")>;
-def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "MXBR$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
+def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
 
 // Multiply and add / subtract
 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
@@ -726,7 +727,7 @@ def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
 // Division
 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
-def : InstRW<[FPU, FPU, Lat30, GroupAlone], (instregex "DXBR$")>;
+def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
 
 //===----------------------------------------------------------------------===//
 // FP: Comparisons
@@ -739,7 +740,7 @@ def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
 
 // Test Data Class
 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
-def : InstRW<[FPU, FPU, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
+def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
 
 }