//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
-#define LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
+#ifndef LLVM_CODEGEN_MIRYAMLMAPPING_H
+#define LLVM_CODEGEN_MIRYAMLMAPPING_H
+#include "llvm/ADT/Optional.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/Support/SMLoc.h"
#include "llvm/Support/YAMLTraits.h"
+#include "llvm/Support/raw_ostream.h"
+#include <algorithm>
+#include <cstdint>
+#include <string>
#include <vector>
namespace llvm {
std::string Value;
SMRange SourceRange;
- StringValue() {}
+ StringValue() = default;
StringValue(std::string Value) : Value(std::move(Value)) {}
bool operator==(const StringValue &Other) const {
};
template <> struct ScalarTraits<StringValue> {
- static void output(const StringValue &S, void *, llvm::raw_ostream &OS) {
+ static void output(const StringValue &S, void *, raw_ostream &OS) {
OS << S.Value;
}
};
struct FlowStringValue : StringValue {
- FlowStringValue() {}
+ FlowStringValue() = default;
FlowStringValue(std::string Value) : StringValue(std::move(Value)) {}
};
template <> struct ScalarTraits<FlowStringValue> {
- static void output(const FlowStringValue &S, void *, llvm::raw_ostream &OS) {
+ static void output(const FlowStringValue &S, void *, raw_ostream &OS) {
return ScalarTraits<StringValue>::output(S, nullptr, OS);
}
struct BlockStringValue {
StringValue Value;
+
bool operator==(const BlockStringValue &Other) const {
return Value == Other.Value;
}
/// A wrapper around unsigned which contains a source range that's being set
/// during parsing.
struct UnsignedValue {
- unsigned Value;
+ unsigned Value = 0;
SMRange SourceRange;
- UnsignedValue() : Value(0) {}
+ UnsignedValue() = default;
UnsignedValue(unsigned Value) : Value(Value) {}
bool operator==(const UnsignedValue &Other) const {
UnsignedValue ID;
StringValue Class;
StringValue PreferredRegister;
+
// TODO: Serialize the target specific register hints.
+
bool operator==(const VirtualRegisterDefinition &Other) const {
return ID == Other.ID && Class == Other.Class &&
PreferredRegister == Other.PreferredRegister;
struct MachineFunctionLiveIn {
StringValue Register;
StringValue VirtualRegister;
+
bool operator==(const MachineFunctionLiveIn &Other) const {
return Register == Other.Register &&
VirtualRegister == Other.VirtualRegister;
StringValue DebugVar;
StringValue DebugExpr;
StringValue DebugLoc;
+
bool operator==(const MachineStackObject &Other) const {
return ID == Other.ID && Name == Other.Name && Type == Other.Type &&
Offset == Other.Offset && Size == Other.Size &&
bool IsImmutable = false;
bool IsAliased = false;
StringValue CalleeSavedRegister;
+
bool operator==(const FixedMachineStackObject &Other) const {
return ID == Other.ID && Type == Other.Type && Offset == Other.Offset &&
Size == Other.Size && Alignment == Other.Alignment &&
StringValue Value;
unsigned Alignment = 0;
bool IsTargetSpecific = false;
+
bool operator==(const MachineConstantPoolValue &Other) const {
return ID == Other.ID && Value == Other.Value &&
Alignment == Other.Alignment &&
struct Entry {
UnsignedValue ID;
std::vector<FlowStringValue> Blocks;
+
bool operator==(const Entry &Other) const {
return ID == Other.ID && Blocks == Other.Blocks;
}
MachineJumpTableInfo::JTEntryKind Kind = MachineJumpTableInfo::EK_Custom32;
std::vector<Entry> Entries;
+
bool operator==(const MachineJumpTable &Other) const {
return Kind == Other.Kind && Entries == Other.Entries;
}
bool HasMustTailInVarArgFunc = false;
StringValue SavePoint;
StringValue RestorePoint;
+
bool operator==(const MachineFrameInfo &Other) const {
return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
IsReturnAddressTaken == Other.IsReturnAddressTaken &&
} // end namespace yaml
} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_MIRYAMLMAPPING_H
-//===--- PreISelIntrinsicLowering.h - Pre-ISel intrinsic lowering pass ----===//
+//===- PreISelIntrinsicLowering.h - Pre-ISel intrinsic lowering pass ------===//
//
// The LLVM Compiler Infrastructure
//
namespace llvm {
+class Module;
+
struct PreISelIntrinsicLoweringPass
: PassInfoMixin<PreISelIntrinsicLoweringPass> {
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
};
-}
+
+} // end namespace llvm
#endif // LLVM_CODEGEN_PREISELINTRINSICLOWERING_H
-//===-- llvm/CodeGen/SelectionDAGAddressAnalysis.h ------- DAG Address Analysis
-//---*- C++ -*-===//
+//===- SelectionDAGAddressAnalysis.h - DAG Address Analysis -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
#ifndef LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
#define LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
-#include "llvm/CodeGen/ISDOpcodes.h"
-#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include <cstdint>
namespace llvm {
+
+class SelectionDAG;
+
/// Helper struct to parse and store a memory address as base + index + offset.
/// We ignore sign extensions when it is safe to do so.
/// The following two expressions are not equivalent. To differentiate we need
private:
SDValue Base;
SDValue Index;
- int64_t Offset;
- bool IsIndexSignExt;
+ int64_t Offset = 0;
+ bool IsIndexSignExt = false;
public:
- BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
-
+ BaseIndexOffset() = default;
BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
bool IsIndexSignExt)
: Base(Base), Index(Index), Offset(Offset),
/// Parses tree in Ptr for base, index, offset addresses.
static BaseIndexOffset match(SDValue Ptr, const SelectionDAG &DAG);
};
-} // namespace llvm
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
-//==-- llvm/CodeGen/SelectionDAGTargetInfo.h - SelectionDAG Info -*- C++ -*-==//
+//==- llvm/CodeGen/SelectionDAGTargetInfo.h - SelectionDAG Info --*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
#ifndef LLVM_CODEGEN_SELECTIONDAGTARGETINFO_H
#define LLVM_CODEGEN_SELECTIONDAGTARGETINFO_H
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Support/CodeGen.h"
+#include <utility>
namespace llvm {
+class SelectionDAG;
+
//===----------------------------------------------------------------------===//
/// Targets can subclass this to parameterize the
/// SelectionDAG lowering and instruction selection process.
///
class SelectionDAGTargetInfo {
- SelectionDAGTargetInfo(const SelectionDAGTargetInfo &) = delete;
- void operator=(const SelectionDAGTargetInfo &) = delete;
-
public:
explicit SelectionDAGTargetInfo() = default;
+ SelectionDAGTargetInfo(const SelectionDAGTargetInfo &) = delete;
+ SelectionDAGTargetInfo &operator=(const SelectionDAGTargetInfo &) = delete;
virtual ~SelectionDAGTargetInfo();
/// Emit target-specific code that performs a memcpy.
MachinePointerInfo SrcPtrInfo) const {
return std::make_pair(SDValue(), SDValue());
}
+
// Return true when the decision to generate FMA's (or FMS, FMLA etc) rather
// than FMUL and ADD is delegated to the machine combiner.
virtual bool generateFMAsInMachineCombiner(CodeGenOpt::Level OptLevel) const {
}
};
-} // end llvm namespace
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_SELECTIONDAGTARGETINFO_H
-//===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
+//===- llvm/CodeGen/VirtRegMap.h - Virtual Register Map ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/ADT/IndexedMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
namespace llvm {
- class MachineInstr;
- class MachineFunction;
- class MachineRegisterInfo;
- class TargetInstrInfo;
- class raw_ostream;
- class SlotIndexes;
+
+class MachineFunction;
+class MachineRegisterInfo;
+class raw_ostream;
+class TargetInstrInfo;
class VirtRegMap : public MachineFunctionPass {
public:
/// createSpillSlot - Allocate a spill slot for RC from MFI.
unsigned createSpillSlot(const TargetRegisterClass *RC);
- VirtRegMap(const VirtRegMap&) = delete;
- void operator=(const VirtRegMap&) = delete;
-
public:
static char ID;
+
VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
- Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) { }
+ Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) {}
+ VirtRegMap(const VirtRegMap &) = delete;
+ VirtRegMap &operator=(const VirtRegMap &) = delete;
+
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
/// @brief create a mapping for the specifed virtual register to
/// the next available stack slot
int assignVirt2StackSlot(unsigned virtReg);
+
/// @brief create a mapping for the specified virtual register to
/// the specified stack slot
void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
VRM.print(OS);
return OS;
}
-} // End llvm namespace
-#endif
+} // end llvm namespace
+
+#endif // LLVM_CODEGEN_VIRTREGMAP_H
-//===-- BranchRelaxation.cpp ----------------------------------------------===//
+//===- BranchRelaxation.cpp -----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <memory>
using namespace llvm;
#define BRANCH_RELAX_NAME "Branch relaxation pass"
namespace {
+
class BranchRelaxation : public MachineFunctionPass {
/// BasicBlockInfo - Information about the offset and size of a single
/// basic block.
/// of this basic block.
///
/// The offset is always aligned as required by the basic block.
- unsigned Offset;
+ unsigned Offset = 0;
/// Size - Size of the basic block in bytes. If the block contains
/// inline assembly, this is a worst case estimate.
///
/// The size does not include any alignment padding whether from the
/// beginning of the block, or from an aligned jump table at the end.
- unsigned Size;
+ unsigned Size = 0;
- BasicBlockInfo() : Offset(0), Size(0) {}
+ BasicBlockInfo() = default;
/// Compute the offset immediately following this block. \p MBB is the next
/// block.
public:
static char ID;
- BranchRelaxation() : MachineFunctionPass(ID) { }
+
+ BranchRelaxation() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
- StringRef getPassName() const override {
- return BRANCH_RELAX_NAME;
- }
+ StringRef getPassName() const override { return BRANCH_RELAX_NAME; }
};
-}
+} // end anonymous namespace
char BranchRelaxation::ID = 0;
+
char &llvm::BranchRelaxationPassID = BranchRelaxation::ID;
INITIALIZE_PASS(BranchRelaxation, DEBUG_TYPE, BRANCH_RELAX_NAME, false, false)
}
}
- /// Insert a new empty basic block and insert it after \BB
+/// Insert a new empty basic block and insert it after \BB
MachineBasicBlock *BranchRelaxation::createNewBlockAfter(MachineBasicBlock &BB) {
// Create a new MBB for the code after the OrigBB.
MachineBasicBlock *NewBB =
// Insert an entry into BlockInfo to align it properly with the block numbers.
BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
-
NewBB->transferSuccessors(OrigBB);
OrigBB->addSuccessor(NewBB);
OrigBB->addSuccessor(DestBB);
-//===-- PreISelIntrinsicLowering.cpp - Pre-ISel intrinsic lowering pass ---===//
+//===- PreISelIntrinsicLowering.cpp - Pre-ISel intrinsic lowering pass ----===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
-#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/User.h"
#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
using namespace llvm;
-namespace {
-
-bool lowerLoadRelative(Function &F) {
+static bool lowerLoadRelative(Function &F) {
if (F.use_empty())
return false;
return Changed;
}
-bool lowerIntrinsics(Module &M) {
+static bool lowerIntrinsics(Module &M) {
bool Changed = false;
for (Function &F : M) {
if (F.getName().startswith("llvm.load.relative."))
return Changed;
}
+namespace {
+
class PreISelIntrinsicLoweringLegacyPass : public ModulePass {
public:
static char ID;
+
PreISelIntrinsicLoweringLegacyPass() : ModulePass(ID) {}
- bool runOnModule(Module &M) { return lowerIntrinsics(M); }
+ bool runOnModule(Module &M) override { return lowerIntrinsics(M); }
};
+} // end anonymous namespace
+
char PreISelIntrinsicLoweringLegacyPass::ID;
-}
INITIALIZE_PASS(PreISelIntrinsicLoweringLegacyPass,
"pre-isel-intrinsic-lowering", "Pre-ISel Intrinsic Lowering",
false, false)
-namespace llvm {
-ModulePass *createPreISelIntrinsicLoweringPass() {
+ModulePass *llvm::createPreISelIntrinsicLoweringPass() {
return new PreISelIntrinsicLoweringLegacyPass;
}
else
return PreservedAnalyses::none();
}
-} // End llvm namespace
-//===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
+//===- RegAllocBase.cpp - Register Allocator Base Class -------------------===//
//
// The LLVM Compiler Infrastructure
//
#include "RegAllocBase.h"
#include "Spiller.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
using namespace llvm;
DEBUG(dbgs() << "\nselectOrSplit "
<< TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
<< ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
- typedef SmallVector<unsigned, 4> VirtRegVec;
+
+ using VirtRegVec = SmallVector<unsigned, 4>;
+
VirtRegVec SplitVRegs;
unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
-//===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
+//===- RegAllocBase.h - basic regalloc interface and driver -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
#ifndef LLVM_LIB_CODEGEN_REGALLOCBASE_H
#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
-#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
namespace llvm {
-template<typename T> class SmallVectorImpl;
-class TargetRegisterInfo;
-class VirtRegMap;
+class LiveInterval;
class LiveIntervals;
class LiveRegMatrix;
+class MachineInstr;
+class MachineRegisterInfo;
+template<typename T> class SmallVectorImpl;
class Spiller;
+class TargetRegisterInfo;
+class VirtRegMap;
/// RegAllocBase provides the register allocation driver and interface that can
/// be extended to add interesting heuristics.
/// assignment order.
class RegAllocBase {
virtual void anchor();
+
protected:
- const TargetRegisterInfo *TRI;
- MachineRegisterInfo *MRI;
- VirtRegMap *VRM;
- LiveIntervals *LIS;
- LiveRegMatrix *Matrix;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ VirtRegMap *VRM = nullptr;
+ LiveIntervals *LIS = nullptr;
+ LiveRegMatrix *Matrix = nullptr;
RegisterClassInfo RegClassInfo;
/// Inst which is a def of an original reg and whose defs are already all
/// always available for the remat of all the siblings of the original reg.
SmallPtrSet<MachineInstr *, 32> DeadRemats;
- RegAllocBase()
- : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
-
- virtual ~RegAllocBase() {}
+ RegAllocBase() = default;
+ virtual ~RegAllocBase() = default;
// A RegAlloc pass should call this before allocatePhysRegs.
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
} // end namespace llvm
-#endif
+#endif // LLVM_LIB_CODEGEN_REGALLOCBASE_H
-//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
+//===- RegAllocFast.cpp - A fast register allocator for debug code --------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseSet.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
-#include "llvm/IR/DebugInfo.h"
+#include "llvm/IR/DebugInfoMetadata.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/Metadata.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetOpcodes.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
-#include <algorithm>
+#include <cassert>
+#include <tuple>
+#include <vector>
+
using namespace llvm;
#define DEBUG_TYPE "regalloc"
fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
namespace {
+
class RegAllocFast : public MachineFunctionPass {
public:
static char ID;
+
RegAllocFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1) {}
private:
/// Everything we know about a live virtual register.
struct LiveReg {
- MachineInstr *LastUse; ///< Last instr to use reg.
- unsigned VirtReg; ///< Virtual register number.
- MCPhysReg PhysReg; ///< Currently held here.
- unsigned short LastOpNum; ///< OpNum on LastUse.
- bool Dirty; ///< Register needs spill.
+ MachineInstr *LastUse = nullptr; ///< Last instr to use reg.
+ unsigned VirtReg; ///< Virtual register number.
+ MCPhysReg PhysReg = 0; ///< Currently held here.
+ unsigned short LastOpNum = 0; ///< OpNum on LastUse.
+ bool Dirty = false; ///< Register needs spill.
- explicit LiveReg(unsigned v)
- : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
+ explicit LiveReg(unsigned v) : VirtReg(v) {}
unsigned getSparseSetIndex() const {
return TargetRegisterInfo::virtReg2Index(VirtReg);
}
};
- typedef SparseSet<LiveReg> LiveRegMap;
+ using LiveRegMap = SparseSet<LiveReg>;
/// This map contains entries for each virtual register that is currently
/// available in a physical register.
LiveRegMap LiveVirtRegs;
- DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
+ DenseMap<unsigned, SmallVector<MachineInstr *, 4>> LiveDbgValueMap;
/// Track the state of a physical register.
enum RegState {
std::vector<unsigned> PhysRegState;
SmallVector<unsigned, 16> VirtDead;
- SmallVector<MachineInstr*, 32> Coalesced;
+ SmallVector<MachineInstr *, 32> Coalesced;
/// Set of register units.
- typedef SparseSet<unsigned> UsedInInstrSet;
+ using UsedInInstrSet = SparseSet<unsigned>;
/// Set of register units that are used in the current instruction, and so
/// cannot be allocated.
spillDirty = 100,
spillImpossible = ~0u
};
+
public:
StringRef getPassName() const override { return "Fast Register Allocator"; }
void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState);
unsigned calcSpillCost(MCPhysReg PhysReg) const;
void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg);
+
LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
}
+
LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
}
+
LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, MCPhysReg PhysReg);
LiveRegMap::iterator allocVirtReg(MachineInstr &MI, LiveRegMap::iterator,
unsigned Hint);
void dumpState();
};
- char RegAllocFast::ID = 0;
-}
+
+} // end anonymous namespace
+
+char RegAllocFast::ID = 0;
INITIALIZE_PASS(RegAllocFast, "regallocfast", "Fast Register Allocator", false,
false)
}
}
-
/// \brief Return the cost of spilling clearing out PhysReg and aliases so it is
/// free for allocation. Returns 0 when PhysReg is free or disabled with all
/// aliases disabled - it can be allocated directly.
return Cost;
}
-
/// \brief This method updates local state so that we know that PhysReg is the
/// proper container for VirtReg now. The physical register must not be used
/// for anything else when this is called.
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/RegisterScavenging.h"
-
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/PassSupport.h"
+#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <iterator>
#include <limits>
#include <string>
+#include <utility>
using namespace llvm;
}
namespace {
+
/// This class runs register scavenging independ of the PrologEpilogInserter.
/// This is used in for testing.
class ScavengerTest : public MachineFunctionPass {
public:
static char ID;
+
ScavengerTest() : MachineFunctionPass(ID) {}
- bool runOnMachineFunction(MachineFunction &MF) {
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetFrameLowering &TFL = *STI.getFrameLowering();
return true;
}
};
-char ScavengerTest::ID;
} // end anonymous namespace
+char ScavengerTest::ID;
+
INITIALIZE_PASS(ScavengerTest, "scavenger-test",
"Scavenge virtual registers inside basic blocks", false, false)
-//===-- SafeStack.cpp - Safe Stack Insertion ------------------------------===//
+//===- SafeStack.cpp - Safe Stack Insertion -------------------------------===//
//
// The LLVM Compiler Infrastructure
//
#include "SafeStackColoring.h"
#include "SafeStackLayout.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/AssumptionCache.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
+#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/Argument.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/CallSite.h"
+#include "llvm/IR/ConstantRange.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DIBuilder.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InstIterator.h"
+#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Use.h"
+#include "llvm/IR/User.h"
+#include "llvm/IR/Value.h"
#include "llvm/Pass.h"
-#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/Format.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Support/raw_os_ostream.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
-#include "llvm/Transforms/Utils/ModuleUtils.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <string>
+#include <utility>
using namespace llvm;
using namespace llvm::safestack;
assert(V == UI.get());
switch (I->getOpcode()) {
- case Instruction::Load: {
+ case Instruction::Load:
if (!IsAccessSafe(UI, DL.getTypeStoreSize(I->getType()), AllocaPtr,
AllocaSize))
return false;
break;
- }
+
case Instruction::VAArg:
// "va-arg" from a pointer is safe.
break;
- case Instruction::Store: {
+ case Instruction::Store:
if (V == I->getOperand(0)) {
// Stored the pointer - conservatively assume it may be unsafe.
DEBUG(dbgs() << "[SafeStack] Unsafe alloca: " << *AllocaPtr
AllocaPtr, AllocaSize))
return false;
break;
- }
- case Instruction::Ret: {
+
+ case Instruction::Ret:
// Information leak.
return false;
- }
case Instruction::Call:
case Instruction::Invoke: {
StackRestorePoints.push_back(LP);
} else if (auto II = dyn_cast<IntrinsicInst>(&I)) {
if (II->getIntrinsicID() == Intrinsic::gcroot)
- llvm::report_fatal_error(
+ report_fatal_error(
"gcroot intrinsic not compatible with safestack attribute");
}
}
}
class SafeStackLegacyPass : public FunctionPass {
- const TargetMachine *TM;
+ const TargetMachine *TM = nullptr;
public:
static char ID; // Pass identification, replacement for typeid..
- SafeStackLegacyPass() : FunctionPass(ID), TM(nullptr) {
+
+ SafeStackLegacyPass() : FunctionPass(ID) {
initializeSafeStackLegacyPassPass(*PassRegistry::getPassRegistry());
}
}
};
-} // anonymous namespace
+} // end anonymous namespace
char SafeStackLegacyPass::ID = 0;
+
INITIALIZE_PASS_BEGIN(SafeStackLegacyPass, DEBUG_TYPE,
"Safe Stack instrumentation pass", false, false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
-//===-- llvm/CodeGen/SelectionDAGAddressAnalysis.cpp ------- DAG Address
-//Analysis ---*- C++ -*-===//
+//==- llvm/CodeGen/SelectionDAGAddressAnalysis.cpp - DAG Address Analysis --==//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Target/TargetLowering.h"
+#include <cstdint>
-namespace llvm {
+using namespace llvm;
bool BaseIndexOffset::equalBaseIndex(BaseIndexOffset &Other,
const SelectionDAG &DAG, int64_t &Off) {
}
return BaseIndexOffset(Base, Index, Offset, IsIndexSignExt);
}
-} // end namespace llvm
-//===-- SelectionDAGTargetInfo.cpp - SelectionDAG Info --------------------===//
+//===- SelectionDAGTargetInfo.cpp - SelectionDAG Info ---------------------===//
//
// The LLVM Compiler Infrastructure
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
using namespace llvm;
-SelectionDAGTargetInfo::~SelectionDAGTargetInfo() {}
+SelectionDAGTargetInfo::~SelectionDAGTargetInfo() = default;
-//===-- ShadowStackGCLowering.cpp - Custom lowering for shadow-stack gc ---===//
+//===- ShadowStackGCLowering.cpp - Custom lowering for shadow-stack gc ----===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
-#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/IR/CallSite.h"
+#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/Constant.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Value.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Transforms/Utils/EscapeEnumerator.h"
+#include <cassert>
+#include <cstddef>
+#include <string>
+#include <utility>
+#include <vector>
using namespace llvm;
class ShadowStackGCLowering : public FunctionPass {
/// RootChain - This is the global linked-list that contains the chain of GC
/// roots.
- GlobalVariable *Head;
+ GlobalVariable *Head = nullptr;
/// StackEntryTy - Abstract type of a link in the shadow stack.
- ///
- StructType *StackEntryTy;
- StructType *FrameMapTy;
+ StructType *StackEntryTy = nullptr;
+ StructType *FrameMapTy = nullptr;
/// Roots - GC roots in the current function. Each is a pair of the
/// intrinsic call and its corresponding alloca.
public:
static char ID;
+
ShadowStackGCLowering();
bool doInitialization(Module &M) override;
Constant *GetFrameMap(Function &F);
Type *GetConcreteStackEntryType(Function &F);
void CollectRoots(Function &F);
+
static GetElementPtrInst *CreateGEP(LLVMContext &Context, IRBuilder<> &B,
Type *Ty, Value *BasePtr, int Idx1,
const char *Name);
Type *Ty, Value *BasePtr, int Idx1, int Idx2,
const char *Name);
};
-}
+
+} // end anonymous namespace
+
+char ShadowStackGCLowering::ID = 0;
INITIALIZE_PASS_BEGIN(ShadowStackGCLowering, DEBUG_TYPE,
"Shadow Stack GC Lowering", false, false)
FunctionPass *llvm::createShadowStackGCLoweringPass() { return new ShadowStackGCLowering(); }
-char ShadowStackGCLowering::ID = 0;
-
-ShadowStackGCLowering::ShadowStackGCLowering()
- : FunctionPass(ID), Head(nullptr), StackEntryTy(nullptr),
- FrameMapTy(nullptr) {
+ShadowStackGCLowering::ShadowStackGCLowering() : FunctionPass(ID) {
initializeShadowStackGCLoweringPass(*PassRegistry::getPassRegistry());
}
-//===-- StackSlotColoring.cpp - Stack slot coloring pass. -----------------===//
+//===- StackSlotColoring.cpp - Stack slot coloring pass. ------------------===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/IR/Module.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <iterator>
#include <vector>
+
using namespace llvm;
#define DEBUG_TYPE "stack-slot-coloring"
STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
namespace {
+
class StackSlotColoring : public MachineFunctionPass {
LiveStacks* LS;
MachineFrameInfo *MFI;
BitVector AllColors;
// NextColor - Next "color" that's not yet used.
- int NextColor;
+ int NextColor = -1;
// UsedColors - "Colors" that have been assigned.
BitVector UsedColors;
public:
static char ID; // Pass identification
- StackSlotColoring() :
- MachineFunctionPass(ID), NextColor(-1) {
- initializeStackSlotColoringPass(*PassRegistry::getPassRegistry());
- }
+
+ StackSlotColoring() : MachineFunctionPass(ID) {
+ initializeStackSlotColoringPass(*PassRegistry::getPassRegistry());
+ }
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
MachineFunction &MF);
bool RemoveDeadStores(MachineBasicBlock* MBB);
};
+
} // end anonymous namespace
char StackSlotColoring::ID = 0;
+
char &llvm::StackSlotColoringID = StackSlotColoring::ID;
INITIALIZE_PASS_BEGIN(StackSlotColoring, DEBUG_TYPE,
"Stack Slot Coloring", false, false)
namespace {
- // IntervalSorter - Comparison predicate that sort live intervals by
- // their weight.
- struct IntervalSorter {
- bool operator()(LiveInterval* LHS, LiveInterval* RHS) const {
- return LHS->weight > RHS->weight;
- }
- };
-}
+
+// IntervalSorter - Comparison predicate that sort live intervals by
+// their weight.
+struct IntervalSorter {
+ bool operator()(LiveInterval* LHS, LiveInterval* RHS) const {
+ return LHS->weight > RHS->weight;
+ }
+};
+
+} // end anonymous namespace
/// ScanForSpillSlotRefs - Scan all the machine instructions for spill slot
/// references and update spill slot weights.
UsedColors.resize(LastFI);
Assignments.resize(LastFI);
- typedef std::iterator_traits<LiveStacks::iterator>::value_type Pair;
+ using Pair = std::iterator_traits<LiveStacks::iterator>::value_type;
+
SmallVector<Pair *, 16> Intervals;
+
Intervals.reserve(LS->getNumIntervals());
for (auto &I : *LS)
Intervals.push_back(&I);
}
/// ColorSlot - Assign a "color" (stack slot) to the specified stack slot.
-///
int StackSlotColoring::ColorSlot(LiveInterval *li) {
int Color = -1;
bool Share = false;
// The MachineMemOperands have already been updated.
}
-
/// RemoveDeadStores - Scan through a basic block and look for loads followed
/// by stores. If they're both using the same stack slot, then the store is
/// definitely dead. This could obviously be much more aggressive (consider
return changed;
}
-
bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) {
DEBUG({
dbgs() << "********** Stack Slot Coloring **********\n"
-//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
+//===- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map -----------------===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/CodeGen/VirtRegMap.h"
#include "LiveDebugVariables.h"
-#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/IR/Function.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
-#include <algorithm>
+#include <cassert>
+#include <iterator>
+#include <utility>
+
using namespace llvm;
#define DEBUG_TYPE "regalloc"
// according to LiveIntervals.
//
namespace {
+
class VirtRegRewriter : public MachineFunctionPass {
MachineFunction *MF;
- const TargetMachine *TM;
const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
MachineRegisterInfo *MRI;
public:
static char ID;
+
VirtRegRewriter() : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override;
+
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
}
};
+
} // end anonymous namespace
+char VirtRegRewriter::ID = 0;
+
char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
"Virtual Register Rewriter", false, false)
-char VirtRegRewriter::ID = 0;
-
void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<LiveIntervals>();
bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
MF = &fn;
- TM = &MF->getTarget();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
MRI = &MF->getRegInfo();
assert(!LI.empty());
assert(LI.hasSubRanges());
- typedef std::pair<const LiveInterval::SubRange *,
- LiveInterval::const_iterator> SubRangeIteratorPair;
+ using SubRangeIteratorPair =
+ std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>;
+
SmallVector<SubRangeIteratorPair, 4> SubRanges;
SlotIndex First;
SlotIndex Last;
projects / llvm / commitdiff