[ReleaseNotes] More X86 updates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@325932 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index 91e7dbb1adf5192903e0a312d5701e345287c8b9..f2bbdc871add4522ce1be4c1c16637d30cf0588c 100644 (file)
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -178,14 +178,34 @@ During this release the X86 target has:
 
 * Added support for Intel Icelake CPU.
 
+* Fixed some X87 codegen bugs.
+
 * Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs.
 
-* Improved codegen of data being transferred between GPRs and K-registers.
+* Improved scheduler model for AMD Jaguar CPUs.
 
 * Improved llvm-mc's disassembler for some EVEX encoded instructions.
 
+* Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions.
+
+* Improved codegen for memory comparisons
+
+* Improved codegen for i32 vector multiplies
+
+* Improved codegen for scalar integer absolute values
+
+* Improved codegen for vector integer rotations (XOP and AVX512)
+
+* Improved codegen of data being transferred between GPRs and K-registers.
+
 * Improved codegen for vector truncations.
 
+* Improved folding of address computations into gather/scatter instructions.
+
+* Gained initial support recognizing variable shuffles from vector element extracts and inserts.
+
+* Improved documentation for SSE/AVX intrinsics in *intrin.h header files.
+
 Changes to the AMDGPU Target
 -----------------------------