[AArch64][GlobalISel] Add default regbank mapping for FP ops.

These should have all their operands - even scalars - go on FPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281737 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index 15aef07a03147981d51edfb8ceb9272a319df207..ab70820e086633f06fe94625421a7a8a51df6021 100644 (file)
--- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -169,6 +169,22 @@ void AArch64RegisterBankInfo::applyMappingImpl(
   }
 }
 
+/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
+/// having only floating-point operands.
+static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
+  switch (Opc) {
+  case TargetOpcode::G_FADD:
+  case TargetOpcode::G_FSUB:
+  case TargetOpcode::G_FMUL:
+  case TargetOpcode::G_FDIV:
+  case TargetOpcode::G_FCONSTANT:
+  case TargetOpcode::G_FPEXT:
+  case TargetOpcode::G_FPTRUNC:
+    return true;
+  }
+  return false;
+}
+
 RegisterBankInfo::InstructionMapping
 AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   const unsigned Opc = MI.getOpcode();
@@ -198,7 +214,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     OpSizes[Idx] = Ty.getSizeInBits();
 
     // As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
-    if (Ty.isVector())
+    // For floating-point instructions, scalars go in FPRs.
+    if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
       OpBanks[Idx] = AArch64::FPRRegBankID;
     else
       OpBanks[Idx] = AArch64::GPRRegBankID;

diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 9fbe25e50feaa3342f2caf903a2369f76d889c52..c8cf12343c6dae9c33df6179cc93b0b00139c3a3 100644 (file)
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -48,6 +48,17 @@
 
   define void @test_load_s32_p0() { ret void }
   define void @test_store_s32_p0() { ret void }
+
+  define void @test_fadd_s32() { ret void }
+  define void @test_fsub_s32() { ret void }
+  define void @test_fmul_s32() { ret void }
+  define void @test_fdiv_s32() { ret void }
+
+  define void @test_fpext_s64_s32() { ret void }
+  define void @test_fptrunc_s32_s64() { ret void }
+
+  define void @test_fconstant_s32() { ret void }
+
 ...
 
 ---
@@ -627,3 +638,131 @@ body: |
     %1(s32) = COPY %w1
     G_STORE %1, %0
 ...
+
+---
+# CHECK-LABEL: name: test_fadd_s32
+name:            test_fadd_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %s0
+    ; CHECK:      %0(s32) = COPY %s0
+    ; CHECK:      %1(s32) = G_FADD %0, %0
+    %0(s32) = COPY %s0
+    %1(s32) = G_FADD %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fsub_s32
+name:            test_fsub_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %s0
+    ; CHECK:      %0(s32) = COPY %s0
+    ; CHECK:      %1(s32) = G_FSUB %0, %0
+    %0(s32) = COPY %s0
+    %1(s32) = G_FSUB %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fmul_s32
+name:            test_fmul_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %s0
+    ; CHECK:      %0(s32) = COPY %s0
+    ; CHECK:      %1(s32) = G_FMUL %0, %0
+    %0(s32) = COPY %s0
+    %1(s32) = G_FMUL %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fdiv_s32
+name:            test_fdiv_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %s0
+    ; CHECK:      %0(s32) = COPY %s0
+    ; CHECK:      %1(s32) = G_FDIV %0, %0
+    %0(s32) = COPY %s0
+    %1(s32) = G_FDIV %0, %0
+...
+
+---
+# CHECK-LABEL: name: test_fpext_s64_s32
+name:            test_fpext_s64_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %s0
+    ; CHECK:      %0(s32) = COPY %s0
+    ; CHECK:      %1(s64) = G_FPEXT %0
+    %0(s32) = COPY %s0
+    %1(s64) = G_FPEXT %0
+...
+
+---
+# CHECK-LABEL: name: test_fptrunc_s32_s64
+name:            test_fptrunc_s32_s64
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+# CHECK:   - { id: 1, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+body: |
+  bb.0:
+    liveins: %d0
+    ; CHECK:      %0(s64) = COPY %d0
+    ; CHECK:      %1(s32) = G_FPTRUNC %0
+    %0(s64) = COPY %d0
+    %1(s32) = G_FPTRUNC %0
+...
+
+---
+# CHECK-LABEL: name: test_fconstant_s32
+name:            test_fconstant_s32
+legalized:       true
+# CHECK: registers:
+# CHECK:   - { id: 0, class: fpr }
+registers:
+  - { id: 0, class: _ }
+body: |
+  bb.0:
+    ; CHECK:      %0(s32) = G_FCONSTANT float 1.0
+    %0(s32) = G_FCONSTANT float 1.0
+...