; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
; AVX128 tests:
}
define <4 x i32> @blend_neg_logic_v4i32(<4 x i32> %a, <4 x i32> %b) {
-; SSE2-LABEL: blend_neg_logic_v4i32:
-; SSE2: # BB#0: # %entry
-; SSE2-NEXT: psrad $31, %xmm1
-; SSE2-NEXT: pxor %xmm1, %xmm0
-; SSE2-NEXT: psubd %xmm1, %xmm0
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: blend_neg_logic_v4i32:
-; SSSE3: # BB#0: # %entry
-; SSSE3-NEXT: psrad $31, %xmm1
-; SSSE3-NEXT: pxor %xmm1, %xmm0
-; SSSE3-NEXT: psubd %xmm1, %xmm0
-; SSSE3-NEXT: retq
-;
-; SSE41-LABEL: blend_neg_logic_v4i32:
-; SSE41: # BB#0: # %entry
-; SSE41-NEXT: psrad $31, %xmm1
-; SSE41-NEXT: pxor %xmm1, %xmm0
-; SSE41-NEXT: psubd %xmm1, %xmm0
-; SSE41-NEXT: retq
+; SSE-LABEL: blend_neg_logic_v4i32:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: psrad $31, %xmm1
+; SSE-NEXT: pxor %xmm1, %xmm0
+; SSE-NEXT: psubd %xmm1, %xmm0
+; SSE-NEXT: retq
;
; AVX-LABEL: blend_neg_logic_v4i32:
; AVX: # BB#0: # %entry
}
define <8 x i32> @blend_neg_logic_v8i32(<8 x i32> %a, <8 x i32> %b) {
-; SSE2-LABEL: blend_neg_logic_v8i32:
-; SSE2: # BB#0: # %entry
-; SSE2-NEXT: psrad $31, %xmm3
-; SSE2-NEXT: psrad $31, %xmm2
-; SSE2-NEXT: pxor %xmm2, %xmm0
-; SSE2-NEXT: psubd %xmm2, %xmm0
-; SSE2-NEXT: pxor %xmm3, %xmm1
-; SSE2-NEXT: psubd %xmm3, %xmm1
-; SSE2-NEXT: retq
-;
-; SSSE3-LABEL: blend_neg_logic_v8i32:
-; SSSE3: # BB#0: # %entry
-; SSSE3-NEXT: psrad $31, %xmm3
-; SSSE3-NEXT: psrad $31, %xmm2
-; SSSE3-NEXT: pxor %xmm2, %xmm0
-; SSSE3-NEXT: psubd %xmm2, %xmm0
-; SSSE3-NEXT: pxor %xmm3, %xmm1
-; SSSE3-NEXT: psubd %xmm3, %xmm1
-; SSSE3-NEXT: retq
-;
-; SSE41-LABEL: blend_neg_logic_v8i32:
-; SSE41: # BB#0: # %entry
-; SSE41-NEXT: psrad $31, %xmm3
-; SSE41-NEXT: psrad $31, %xmm2
-; SSE41-NEXT: pxor %xmm2, %xmm0
-; SSE41-NEXT: psubd %xmm2, %xmm0
-; SSE41-NEXT: pxor %xmm3, %xmm1
-; SSE41-NEXT: psubd %xmm3, %xmm1
-; SSE41-NEXT: retq
+; SSE-LABEL: blend_neg_logic_v8i32:
+; SSE: # BB#0: # %entry
+; SSE-NEXT: psrad $31, %xmm3
+; SSE-NEXT: psrad $31, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: psubd %xmm2, %xmm0
+; SSE-NEXT: pxor %xmm3, %xmm1
+; SSE-NEXT: psubd %xmm3, %xmm1
+; SSE-NEXT: retq
;
; AVX1-LABEL: blend_neg_logic_v8i32:
; AVX1: # BB#0: # %entry