/* Register hinting (a cheap way for register coalescing) */
for (i = 0; i < ssa->vars_count; i++) {
if (intervals[i]) {
- int var = intervals[i]->ssa_var;
int src;
- if (ssa->vars[var].definition_phi) {
- zend_ssa_phi *phi = ssa->vars[var].definition_phi;
+ if (ssa->vars[i].definition_phi) {
+ zend_ssa_phi *phi = ssa->vars[i].definition_phi;
if (phi->pi >= 0) {
src = phi->sources[0];
}
for (i = 0; i < ssa->vars_count; i++) {
if (intervals[i] && !intervals[i]->hint) {
- int var = intervals[i]->ssa_var;
- if (ssa->vars[var].definition >= 0) {
- uint32_t line = ssa->vars[var].definition;
+ if (ssa->vars[i].definition >= 0) {
+ uint32_t line = ssa->vars[i].definition;
const zend_op *opline = op_array->opcodes + line;
switch (opline->opcode) {
case ZEND_POST_DEC:
if (ssa->ops[line].op1_use >= 0 &&
intervals[ssa->ops[line].op1_use] &&
- (var == ssa->ops[line].op1_def ||
- (var == ssa->ops[line].result_def &&
+ (i == ssa->ops[line].op1_def ||
+ (i == ssa->ops[line].result_def &&
(ssa->ops[line].op1_def < 0 ||
!intervals[ssa->ops[line].op1_def])))) {
zend_jit_add_hint(intervals, i, ssa->ops[line].op1_use);
case ZEND_SEND_VAR:
case ZEND_PRE_INC:
case ZEND_PRE_DEC:
- if (var == ssa->ops[line].op1_def &&
+ if (i == ssa->ops[line].op1_def &&
ssa->ops[line].op1_use >= 0 &&
intervals[ssa->ops[line].op1_use]) {
zend_jit_add_hint(intervals, i, ssa->ops[line].op1_use);
case ZEND_ASSIGN:
if (ssa->ops[line].op2_use >= 0 &&
intervals[ssa->ops[line].op2_use] &&
- (var == ssa->ops[line].op2_def ||
- (var == ssa->ops[line].op1_def &&
+ (i == ssa->ops[line].op2_def ||
+ (i == ssa->ops[line].op1_def &&
(ssa->ops[line].op2_def < 0 ||
!intervals[ssa->ops[line].op2_def])) ||
- (var == ssa->ops[line].result_def &&
+ (i == ssa->ops[line].result_def &&
(ssa->ops[line].op2_def < 0 ||
!intervals[ssa->ops[line].op2_def]) &&
(ssa->ops[line].op1_def < 0 ||