--- /dev/null
+menu "EspAudio"
+
+config AUDIO_LOG_ERROR_EN
+ bool "Enable Audio error message"
+ default y
+ help
+ Disable it will redurce error information and run faster
+config AUDIO_LOG_WARN_EN
+ bool "Enable Audio warning message"
+ default y
+ help
+ Disable it will redurce warning information and run faster
+config AUDIO_LOG_INFO_EN
+ bool "Enable Audio normal message"
+ default y
+ help
+ Disable it will redurce normal information and run faster
+config AUDIO_LOG_DEBUG_EN
+ bool "Enable Audio debug message"
+ default n
+ help
+ Disable it will redurce debug information and run faster
+
+endmenu
--- /dev/null
+Date：2016-11-14\r
+更新内容:\r
+1.Recorder 支持PCM,实现录音回放的demo, 16k,16bit;\r
+2.fix 播放破音bug;\r
+3.优化按键Key为中断方式;\r
+4. API修改：EspAudioPlayerDataWrite->EspAudioPlayerStreamWrite\r
+5. API新增：EspAudioPlayerStreamCfg(uint32_t rate, uint32_t channel,uint32_t bitLen)\r
+\r
+\r
+Date：2016-11-04\r
+新增功能:\r
+1.Airpaly\r
+2.DLNA\r
+\r
+Date:2016-10-14\r
+\r
+Espressif Audio Player Library 0.5.1\r
+支持功能:\r
+1. URL播放音乐和播控\r
+2. 音频支持MP3、AAC、FLAC、WAV\r
+\r
--- /dev/null
+#
+# Component Makefile
+#
+# This Makefile should, at the very least, just include $(IDF_PATH)/make/component_common.mk. By default,
+# this will take the sources in this directory, compile them and link them into
+# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
+# please read the esp-idf build system document if you need to do this.
+#
+LIBS := esp_audio
+
+COMPONENT_ADD_INCLUDEDIRS := include include/driver
+
+COMPONENT_ADD_LDFLAGS := \
+ $(abspath lib/libEspAudio.a) \
+ $(abspath lib/libMisc.a) \
+ $(abspath lib/libMediaHal.a) \
+ $(abspath lib/libdlna.a) \
+
+include $(IDF_PATH)/make/component_common.mk
+
+
+# this is a hack to make sure the app is re-linked if the binary
+# libraries change or are updated. If they change, the main esp32
+# library will be rebuild by AR andthis will trigger a re-linking of
+# the entire app.
+#
+# It would be better for components to be able to expose any of these
+# non-standard dependencies via get_variable, but this will do for now.
+$(COMPONENT_LIBRARY): $(ALL_LIB_FILES)
--- /dev/null
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+\r
+#ifndef ESP_AUDIO\r
+#define ESP_AUDIO\r
+#include "esp_types.h"\r
+#include "EspAudioCom.h"\r
+\r
+\r
+\r
+/*\r
+ * Maximum size of the URI, including null character.\r
+ */\r
+#define MAX_URI_SIZE 1024\r
+\r
+/*\r
+ * Defines various states that the ESP player can be.\r
+ */\r
+enum EspAudioState\r
+{\r
+ AUDIOSTATE_UNINITIALIZED = 0, /* player is not initialized */\r
+ AUDIOSTATE_IDLE, /* player is idle */\r
+ AUDIOSTATE_STOPPED, /* player is stopled */\r
+ AUDIOSTATE_TRANSIT, /* player is busy in a transition */\r
+ AUDIOSTATE_PLAYING, /* player is currently playing */\r
+ AUDIOSTATE_PAUSED, /* player is in the paused state for playback */\r
+ AUDIOSTATE_ENDED, /* player finished decoding player, without user request. */\r
+ AUDIOSTATE_ERROR, /* player was given a URI that could not be played */\r
+\r
+ AUDIOSTATE_UNKNOWN /* unknown playstate */\r
+};\r
+\r
+\r
+typedef enum\r
+{\r
+ InputSrcType_NetSpec = 0, ///< Specify audio file from internet.\r
+ InputSrcType_NetLiving = 1, ///< Living audio stream from internet,e.g.m3u8\r
+ InputSrcType_LocalFile = 2, ///< Local file which store in the SD card\r
+ InputSrcType_Stream = 3, ///< Only audio stream,e.g.PCM\r
+ InputSrcType_Max\r
+} InputSrcType;\r
+\r
+\r
+typedef enum\r
+{\r
+ EspAudioErr_NoErr =0, ///< No error\r
+ EspAudioErr_InvalidPara, ///< Invalid parameters\r
+ EspAudioErr_NoMem, ///< Malloc failed\r
+ EspAudioErr_HardwareErr, ///< Hardware error\r
+ EspAudioErr_OutOfRange, ///< length of URI is too long.\r
+ EspAudioErr_NotSupport, ///< Not support the\r
+\r
+} EspAudioErr;\r
+\r
+\r
+/*\r
+ * Initializes the ESP player library.\r
+ */\r
+void EspAudio_Init(void);\r
+\r
+/*\r
+ * Cleans up the ESP player library.\r
+ */\r
+void EspAudio_UnInit(void);\r
+\r
+/*\r
+ * Play, stop, pause the streaming and output of player\r
+ * EspAudio_Init must be called before these methods work.\r
+ */\r
+int EspAudio_SetupStream(const char* URI, InputSrcType UriType);\r
+/*\r
+ * Call this method to transition to playing state.\r
+ *\r
+ * Returns nonzero if an error occurred.\r
+ */\r
+int EspAudio_Play(void);\r
+\r
+/*\r
+ * Call this method to stop playing ESP player.\r
+ *\r
+ * Returns nonzero if an error occurred.\r
+ */\r
+int EspAudio_Stop(void);\r
+\r
+/*\r
+ * Call this method to pause the playing ESP player.\r
+ *\r
+ * Returns nonzero if an error occurred.\r
+ */\r
+int EspAudio_Pause(void);\r
+\r
+/*\r
+ * Returns the playstate of the ESP player library.\r
+ * Returns MEDIA_UNKNOWN if the stream could not be found.\r
+ */\r
+enum EspAudioState EspAudio_GetPlayState(void);\r
+\r
+/*\r
+ * Get the player volume level . Volume level is from 0 to 100.\r
+ * Returns a negative value if the stream could not be found or the value is unknown.\r
+ */\r
+int EspAudio_GetVolume(int *level);\r
+\r
+/*\r
+ * Set the player volume level . Volume level is from 0 to 100.\r
+ * Returns a negative value if the stream could not be found or the value is unknown.\r
+ */\r
+int EspAudio_SetVolume(int level);\r
+\r
+/*\r
+ * Call this method to configrate stream information.\r
+ *\r
+ * Returns nonzero if an error occurred.\r
+ */\r
+EspAudioErr EspAudioPlayerStreamCfg(uint32_t rate, uint32_t channel,uint32_t bitLen);\r
+\r
+/*\r
+ * Call this method to flush stream data to driver.\r
+ *\r
+ * Returns nonzero if an error occurred.\r
+ */\r
+EspAudioErr EspAudioPlayerStreamWrite(uint8_t *inData, uint32_t inSize);\r
+\r
+\r
+#endif\r
--- /dev/null
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+\r
+#ifndef _ESPAUDIOCOM_H\r
+#define _ESPAUDIOCOM_H\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "audio_log.h"\r
+#include "EspAudioCom.h"\r
+\r
+#define ESP_AUDIO_RELEASE_MAJOR (0000)\r
+#define ESP_AUDIO_RELEASE_MINOR (51)\r
+#define ESP_AUDIO_RELEASE_VER "0.51"\r
+\r
+\r
+typedef struct\r
+{\r
+ uint32_t type;\r
+ char str[256];\r
+} UrlInfo;\r
+\r
+\r
+typedef enum {\r
+ StreamType_Opus,\r
+ StreamType_Pcm, // it will be support\r
+ StreamType_Max,\r
+} StreamType;\r
+\r
+\r
+typedef enum {\r
+ StreamSampleRate_8k = 8000, \r
+ StreamSampleRate_16k = 16000, // This is support\r
+ StreamSampleRate_22K = 22050,\r
+ StreamSampleRate_32K = 32000,\r
+ StreamSampleRate_44k = 44100,\r
+ StreamSampleRate_48k = 48000,\r
+ StreamSampleRate_Max,\r
+} StreamSampleRate;\r
+\r
+\r
+typedef enum {
+ StreamBitLen_8BIT = 8,\r
+ StreamBitLen_16BIT = 16,\r
+ StreamBitLen_24BIT = 24,\r
+ StreamBitLen_32BIT = 32,\r
+ StreamBitLen_Max,\r
+} StreamBitLen;\r
+\r
+\r
+typedef enum {\r
+ StreamChannel_One, // it will be support\r
+ StreamChannel_Two,\r
+ StreamChannel_Max,\r
+} StreamChannel;\r
+\r
+#endif /* _ESPAUDIOCOM_H */
\ No newline at end of file
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+\r
+#ifndef __ESPAUDIORECORDER_H__\r
+#define __ESPAUDIORECORDER_H__\r
+#include "esp_types.h"\r
+#include "EspAudio.h"\r
+\r
+\r
+//Type Definitions\r
+typedef void (*Callback_RecordData)(void *recBuf, uint32_t *recLen);\r
+\r
+typedef enum {\r
+ RecorderState_Unknown = 0,\r
+ RecorderState_Init,\r
+ RecorderState_Stoped,\r
+ RecorderState_Recording,\r
+ RecorderState_Paused,\r
+} RecorderState;\r
+\r
+typedef enum {\r
+ EncodeType_Opus = 1,\r
+ EncodeType_Pcm, // it will be support\r
+ EncodeType_Max,\r
+} EncodeType;\r
+\r
+\r
+typedef enum {\r
+ RecorderSampleRate_8k = 8000, // it will be support\r
+ RecorderSampleRate_16k = 16000,\r
+ RecorderSampleRate_Max,\r
+} RecorderSampleRate;\r
+\r
+\r
+typedef enum {\r
+ RecorderChannel_One = 1, // it will be support\r
+ RecorderChannel_Two,\r
+ RecorderChannel_Max,\r
+} RecorderChannel;\r
+\r
+\r
+typedef struct {\r
+ RecorderSampleRate rate;\r
+ RecorderChannel channel;\r
+ EncodeType encodeType;\r
+ Callback_RecordData func;\r
+} RecorderAttr;\r
+\r
+\r
+EspAudioErr EspAudioRecorderStart(RecorderAttr *recorderAttr);\r
+EspAudioErr EspAudioRecorderStop(void);\r
+EspAudioErr EspAudioRecorderPause(void);\r
+EspAudioErr EspAudioRecorderResume(void);\r
+EspAudioErr EspAudioRecorderStateGet(RecorderState *state);\r
+EspAudioErr EspAudioRecorderInit(void);\r
+EspAudioErr EspAudioRecorderUninit(void);\r
+\r
+\r
+#endif //__ESPAUDIORECORDER_H__\r
--- /dev/null
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+\r
+#ifndef __AUDIO_LOG_H__\r
+#define __AUDIO_LOG_H__\r
+#include "esp_types.h"\r
+#include "sdkconfig.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Make sure all of the definitions in this header have a C binding.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+void __log(const char *level, const char * func, uint32_t line, const char * restrict format, ...);\r
+\r
+#ifdef CONFIG_AUDIO_LOG_INFO_EN\r
+#define LOGI(format, ...) __log("I", __func__, __LINE__, format, ##__VA_ARGS__);\r
+#else\r
+#define LOGI(format, ...)\r
+#endif\r
+\r
+#ifdef CONFIG_AUDIO_LOG_DEBUG_EN\r
+#define LOGD(format, ...) __log("D", __func__, __LINE__, format, ##__VA_ARGS__);\r
+#else\r
+#define LOGD(format, ...)\r
+#endif\r
+\r
+#ifdef CONFIG_AUDIO_LOG_WARN_EN\r
+#define LOGW(format, ...) __log("W", __func__, __LINE__, format, ##__VA_ARGS__);\r
+#else\r
+#define LOGW(format, ...)\r
+#endif\r
+\r
+#ifdef CONFIG_AUDIO_LOG_ERROR_EN\r
+#define LOGE(format, ...) __log("E", __func__, __LINE__, format, ##__VA_ARGS__);\r
+#else\r
+#define LOGE(format, ...)\r
+#endif\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __AUDIO_LOG_H__\r
--- /dev/null
+#ifndef _DNLA_H_
+#define _DNLA_H_
+typedef enum {
+ DLNA_INIT,
+ DLNA_START,
+ DLNA_STOP,
+ DLNA_MEDIA_PLAYING,
+ DLNA_MEDIA_PAUSED,
+ DLNA_MEDIA_ERROR,
+ DLNA_MEDIA_STOPPED,
+ DLNA_MEDIA_ENDED,
+ DLNA_UNINIT
+} EspDlnaState;
+
+
+typedef void (*dnlaStateCallback)(EspDlnaState state);
+
+typedef enum {
+ ESPDLNA_ERROR = -1,
+ ESPDLNA_OK = 0
+} EspDlnaErr;
+
+typedef struct {
+ char FriendlyName[128];
+ char UDN[64];
+ char SerialNumber[64];
+ int NotifyCycleSeconds;
+ unsigned short PortNum;
+} EspDlnaAttr;
+
+void dlna_task(void *pvParameters);
+EspDlnaErr EspDlnaInit(EspDlnaAttr *attr, dnlaStateCallback cb);
+EspDlnaErr EspDlnaUnInit(void);
+EspDlnaErr EspDlnaStart(void);
+EspDlnaErr EspDlnaStop(void);
+#endif
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_DMA_H_
+#define _DRIVER_DMA_H__
+#include <esp_types.h>
+
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup Driver_APIs Driver APIs
+ * @brief Driver APIs
+ */
+
+/** @addtogroup Driver_APIs
+ * @{
+ */
+
+/**
+ * @brief DMA queue description.
+ */
+typedef struct {
+ uint32_t block_size: 12;
+ uint32_t data_length: 12;
+ uint32_t unused: 5;
+ uint32_t sub_sof: 1;
+ uint32_t eof: 1;
+ uint32_t owner: 1;
+ uint32_t buf_ptr;
+ uint32_t next_link_ptr;
+} dma_queue_t;
+
+/**
+ * @brief DMA element description
+ */
+typedef struct {
+ uint32_t *buffer_addr;
+ dma_queue_t *first_queue;
+ dma_queue_t *last_queue;
+ dma_queue_t backup_queue;
+} dma_element_t;
+
+/**
+ * @brief DMA ping-pong buffer object description
+ */
+typedef struct {
+ dma_element_t *ping;
+ dma_element_t *pong;
+ uint32_t len;
+ uint32_t queue_cnt;
+} ping_pong_buf_t;
+
+
+/**
+ * @brief Create a ping-pong buffer object used by DMA.
+ *
+ * @param [in] bufLen
+ * Set the buffer length.
+ * --------------------
+ * | ping | Pong |
+ * --------------------
+ * | bufLen | bufLen |
+ * --------------------
+ *
+ * @return uint32*, NULL:indicates parameter error, others indicates ping-pong buffer address.
+ */
+ping_pong_buf_t* dma_buf_create(uint32_t bufLen);
+
+/**
+ * @brief Reset the dma buffer length.
+ *
+ * @param [in] obj
+ * Pointer to a struct ping_pong_buf_t that indicates the object length to be reset to bufLen.
+ *
+ * @return uint32*, ESP_FAIL:indicates parameter error, ESP_OK :indicates success.
+ */
+esp_err_t dma_buf_len_reset(ping_pong_buf_t *obj);
+
+/**
+ * @brief Set the buffer length before the start.
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t.
+ * @param [in] len
+ * Set the transmit length .
+ *
+ * @return uint32*, ESP_FAIL:indicates parameter error, ESP_OK: indicates success.
+ */
+esp_err_t dma_buf_len_set(ping_pong_buf_t *obj, dma_element_t *element, uint32_t len);
+
+/**
+ * @brief Destroy the ping-pong buffer instance.
+ *
+ * @param [in] obj
+ * Pointer to a struct ping_pong_buf_t that indicates the object to be destroy.
+ *
+ * @return NULL
+ */
+void dma_buf_destroy(ping_pong_buf_t *obj);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DMA_H__
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_GPIO_SIG_MAP_H_
+#define _DRIVER_GPIO_SIG_MAP_H_
+
+#define SPICLK_IN_IDX 0
+#define SPICLK_OUT_IDX 0
+#define SPIQ_IN_IDX 1
+#define SPIQ_OUT_IDX 1
+#define SPID_IN_IDX 2
+#define SPID_OUT_IDX 2
+#define SPIHD_IN_IDX 3
+#define SPIHD_OUT_IDX 3
+#define SPIWP_IN_IDX 4
+#define SPIWP_OUT_IDX 4
+#define SPICS0_IN_IDX 5
+#define SPICS0_OUT_IDX 5
+#define SPICS1_IN_IDX 6
+#define SPICS1_OUT_IDX 6
+#define SPICS2_IN_IDX 7
+#define SPICS2_OUT_IDX 7
+#define HSPICLK_IN_IDX 8
+#define HSPICLK_OUT_IDX 8
+#define HSPIQ_IN_IDX 9
+#define HSPIQ_OUT_IDX 9
+#define HSPID_IN_IDX 10
+#define HSPID_OUT_IDX 10
+#define HSPICS0_IN_IDX 11
+#define HSPICS0_OUT_IDX 11
+#define HSPIHD_IN_IDX 12
+#define HSPIHD_OUT_IDX 12
+#define HSPIWP_IN_IDX 13
+#define HSPIWP_OUT_IDX 13
+#define U0RXD_IN_IDX 14
+#define U0TXD_OUT_IDX 14
+#define U0CTS_IN_IDX 15
+#define U0RTS_OUT_IDX 15
+#define U0DSR_IN_IDX 16
+#define U0DTR_OUT_IDX 16
+#define U1RXD_IN_IDX 17
+#define U1TXD_OUT_IDX 17
+#define U1CTS_IN_IDX 18
+#define U1RTS_OUT_IDX 18
+#define I2CM_SCL_O_IDX 19
+#define I2CM_SDA_I_IDX 20
+#define I2CM_SDA_O_IDX 20
+#define EXT_I2C_SCL_O_IDX 21
+#define EXT_I2C_SDA_O_IDX 22
+#define EXT_I2C_SDA_I_IDX 22
+#define I2S0O_BCK_IN_IDX 23
+#define I2S0O_BCK_OUT_IDX 23
+#define I2S1O_BCK_IN_IDX 24
+#define I2S1O_BCK_OUT_IDX 24
+#define I2S0O_WS_IN_IDX 25
+#define I2S0O_WS_OUT_IDX 25
+#define I2S1O_WS_IN_IDX 26
+#define I2S1O_WS_OUT_IDX 26
+#define I2S0I_BCK_IN_IDX 27
+#define I2S0I_BCK_OUT_IDX 27
+#define I2S0I_WS_IN_IDX 28
+#define I2S0I_WS_OUT_IDX 28
+#define I2CEXT0_SCL_IN_IDX 29
+#define I2CEXT0_SCL_OUT_IDX 29
+#define I2CEXT0_SDA_IN_IDX 30
+#define I2CEXT0_SDA_OUT_IDX 30
+#define PWM0_SYNC0_IN_IDX 31
+#define SDIO_TOHOST_INT_OUT_IDX 31
+#define PWM0_SYNC1_IN_IDX 32
+#define PWM0_OUT0A_IDX 32
+#define PWM0_SYNC2_IN_IDX 33
+#define PWM0_OUT0B_IDX 33
+#define PWM0_F0_IN_IDX 34
+#define PWM0_OUT1A_IDX 34
+#define PWM0_F1_IN_IDX 35
+#define PWM0_OUT1B_IDX 35
+#define PWM0_F2_IN_IDX 36
+#define PWM0_OUT2A_IDX 36
+#define GPIO_BT_ACTIVE_IDX 37
+#define PWM0_OUT2B_IDX 37
+#define GPIO_BT_PRIORITY_IDX 38
+#define PCNT_SIG_CH0_IN0_IDX 39
+#define PCNT_SIG_CH1_IN0_IDX 40
+#define GPIO_WLAN_ACTIVE_IDX 40
+#define PCNT_CTRL_CH0_IN0_IDX 41
+#define BB_DIAG0_IDX 41
+#define PCNT_CTRL_CH1_IN0_IDX 42
+#define BB_DIAG1_IDX 42
+#define PCNT_SIG_CH0_IN1_IDX 43
+#define BB_DIAG2_IDX 43
+#define PCNT_SIG_CH1_IN1_IDX 44
+#define BB_DIAG3_IDX 44
+#define PCNT_CTRL_CH0_IN1_IDX 45
+#define BB_DIAG4_IDX 45
+#define PCNT_CTRL_CH1_IN1_IDX 46
+#define BB_DIAG5_IDX 46
+#define PCNT_SIG_CH0_IN2_IDX 47
+#define BB_DIAG6_IDX 47
+#define PCNT_SIG_CH1_IN2_IDX 48
+#define BB_DIAG7_IDX 48
+#define PCNT_CTRL_CH0_IN2_IDX 49
+#define BB_DIAG8_IDX 49
+#define PCNT_CTRL_CH1_IN2_IDX 50
+#define BB_DIAG9_IDX 50
+#define PCNT_SIG_CH0_IN3_IDX 51
+#define BB_DIAG10_IDX 51
+#define PCNT_SIG_CH1_IN3_IDX 52
+#define BB_DIAG11_IDX 52
+#define PCNT_CTRL_CH0_IN3_IDX 53
+#define BB_DIAG12_IDX 53
+#define PCNT_CTRL_CH1_IN3_IDX 54
+#define BB_DIAG13_IDX 54
+#define PCNT_SIG_CH0_IN4_IDX 55
+#define BB_DIAG14_IDX 55
+#define PCNT_SIG_CH1_IN4_IDX 56
+#define BB_DIAG15_IDX 56
+#define PCNT_CTRL_CH0_IN4_IDX 57
+#define BB_DIAG16_IDX 57
+#define PCNT_CTRL_CH1_IN4_IDX 58
+#define BB_DIAG17_IDX 58
+#define BB_DIAG18_IDX 59
+#define BB_DIAG19_IDX 60
+#define HSPICS1_IN_IDX 61
+#define HSPICS1_OUT_IDX 61
+#define HSPICS2_IN_IDX 62
+#define HSPICS2_OUT_IDX 62
+#define VSPICLK_IN_IDX 63
+#define VSPICLK_OUT_MUX_IDX 63
+#define VSPIQ_IN_IDX 64
+#define VSPIQ_OUT_IDX 64
+#define VSPID_IN_IDX 65
+#define VSPID_OUT_IDX 65
+#define VSPIHD_IN_IDX 66
+#define VSPIHD_OUT_IDX 66
+#define VSPIWP_IN_IDX 67
+#define VSPIWP_OUT_IDX 67
+#define VSPICS0_IN_IDX 68
+#define VSPICS0_OUT_IDX 68
+#define VSPICS1_IN_IDX 69
+#define VSPICS1_OUT_IDX 69
+#define VSPICS2_IN_IDX 70
+#define VSPICS2_OUT_IDX 70
+#define PCNT_SIG_CH0_IN5_IDX 71
+#define LEDC_HS_SIG_OUT0_IDX 71
+#define PCNT_SIG_CH1_IN5_IDX 72
+#define LEDC_HS_SIG_OUT1_IDX 72
+#define PCNT_CTRL_CH0_IN5_IDX 73
+#define LEDC_HS_SIG_OUT2_IDX 73
+#define PCNT_CTRL_CH1_IN5_IDX 74
+#define LEDC_HS_SIG_OUT3_IDX 74
+#define PCNT_SIG_CH0_IN6_IDX 75
+#define LEDC_HS_SIG_OUT4_IDX 75
+#define PCNT_SIG_CH1_IN6_IDX 76
+#define LEDC_HS_SIG_OUT5_IDX 76
+#define PCNT_CTRL_CH0_IN6_IDX 77
+#define LEDC_HS_SIG_OUT6_IDX 77
+#define PCNT_CTRL_CH1_IN6_IDX 78
+#define LEDC_HS_SIG_OUT7_IDX 78
+#define PCNT_SIG_CH0_IN7_IDX 79
+#define LEDC_LS_SIG_OUT0_IDX 79
+#define PCNT_SIG_CH1_IN7_IDX 80
+#define LEDC_LS_SIG_OUT1_IDX 80
+#define PCNT_CTRL_CH0_IN7_IDX 81
+#define LEDC_LS_SIG_OUT2_IDX 81
+#define PCNT_CTRL_CH1_IN7_IDX 82
+#define LEDC_LS_SIG_OUT3_IDX 82
+#define RMT_SIG_IN0_IDX 83
+#define LEDC_LS_SIG_OUT4_IDX 83
+#define RMT_SIG_IN1_IDX 84
+#define LEDC_LS_SIG_OUT5_IDX 84
+#define RMT_SIG_IN2_IDX 85
+#define LEDC_LS_SIG_OUT6_IDX 85
+#define RMT_SIG_IN3_IDX 86
+#define LEDC_LS_SIG_OUT7_IDX 86
+#define RMT_SIG_IN4_IDX 87
+#define RMT_SIG_OUT0_IDX 87
+#define RMT_SIG_IN5_IDX 88
+#define RMT_SIG_OUT1_IDX 88
+#define RMT_SIG_IN6_IDX 89
+#define RMT_SIG_OUT2_IDX 89
+#define RMT_SIG_IN7_IDX 90
+#define RMT_SIG_OUT3_IDX 90
+#define RMT_SIG_OUT4_IDX 91
+#define RMT_SIG_OUT5_IDX 92
+#define EXT_ADC_START_IDX 93
+#define RMT_SIG_OUT6_IDX 93
+#define CAN_RX_IDX 94
+#define RMT_SIG_OUT7_IDX 94
+#define I2CEXT1_SCL_IN_IDX 95
+#define I2CEXT1_SCL_OUT_IDX 95
+#define I2CEXT1_SDA_IN_IDX 96
+#define I2CEXT1_SDA_OUT_IDX 96
+#define HOST_CARD_DETECT_N_1_IDX 97
+#define HOST_CCMD_OD_PULLUP_EN_N_IDX 97
+#define HOST_CARD_DETECT_N_2_IDX 98
+#define HOST_RST_N_1_IDX 98
+#define HOST_CARD_WRITE_PRT_1_IDX 99
+#define HOST_RST_N_2_IDX 99
+#define HOST_CARD_WRITE_PRT_2_IDX 100
+#define GPIO_SD0_OUT_IDX 100
+#define HOST_CARD_INT_N_1_IDX 101
+#define GPIO_SD1_OUT_IDX 101
+#define HOST_CARD_INT_N_2_IDX 102
+#define GPIO_SD2_OUT_IDX 102
+#define PWM1_SYNC0_IN_IDX 103
+#define GPIO_SD3_OUT_IDX 103
+#define PWM1_SYNC1_IN_IDX 104
+#define GPIO_SD4_OUT_IDX 104
+#define PWM1_SYNC2_IN_IDX 105
+#define GPIO_SD5_OUT_IDX 105
+#define PWM1_F0_IN_IDX 106
+#define GPIO_SD6_OUT_IDX 106
+#define PWM1_F1_IN_IDX 107
+#define GPIO_SD7_OUT_IDX 107
+#define PWM1_F2_IN_IDX 108
+#define PWM1_OUT0A_IDX 108
+#define PWM0_CAP0_IN_IDX 109
+#define PWM1_OUT0B_IDX 109
+#define PWM0_CAP1_IN_IDX 110
+#define PWM1_OUT1A_IDX 110
+#define PWM0_CAP2_IN_IDX 111
+#define PWM1_OUT1B_IDX 111
+#define PWM1_CAP0_IN_IDX 112
+#define PWM1_OUT2A_IDX 112
+#define PWM1_CAP1_IN_IDX 113
+#define PWM1_OUT2B_IDX 113
+#define PWM1_CAP2_IN_IDX 114
+#define PWM2_OUT1H_IDX 114
+#define PWM2_FLTA_IDX 115
+#define PWM2_OUT1L_IDX 115
+#define PWM2_FLTB_IDX 116
+#define PWM2_OUT2H_IDX 116
+#define PWM2_CAP1_IN_IDX 117
+#define PWM2_OUT2L_IDX 117
+#define PWM2_CAP2_IN_IDX 118
+#define PWM2_OUT3H_IDX 118
+#define PWM2_CAP3_IN_IDX 119
+#define PWM2_OUT3L_IDX 119
+#define PWM3_FLTA_IDX 120
+#define PWM2_OUT4H_IDX 120
+#define PWM3_FLTB_IDX 121
+#define PWM2_OUT4L_IDX 121
+#define PWM3_CAP1_IN_IDX 122
+#define PWM3_CAP2_IN_IDX 123
+#define CAN_TX_IDX 123
+#define PWM3_CAP3_IN_IDX 124
+#define CAN_BUS_OFF_ON_IDX 124
+#define ATCK_IN_IDX 125
+#define CAN_CLKOUT_IDX 125
+#define ATMS_IN_IDX 126
+#define ATDI_IN_IDX 127
+#define ATDO_OUT_IDX 127
+#define SPID4_IN_IDX 128
+#define SPID4_OUT_IDX 128
+#define SPID5_IN_IDX 129
+#define SPID5_OUT_IDX 129
+#define SPID6_IN_IDX 130
+#define SPID6_OUT_IDX 130
+#define SPID7_IN_IDX 131
+#define SPID7_OUT_IDX 131
+#define HSPID4_IN_IDX 132
+#define HSPID4_OUT_IDX 132
+#define HSPID5_IN_IDX 133
+#define HSPID5_OUT_IDX 133
+#define HSPID6_IN_IDX 134
+#define HSPID6_OUT_IDX 134
+#define HSPID7_IN_IDX 135
+#define HSPID7_OUT_IDX 135
+#define VSPID4_IN_IDX 136
+#define VSPID4_OUT_IDX 136
+#define VSPID5_IN_IDX 137
+#define VSPID5_OUT_IDX 137
+#define VSPID6_IN_IDX 138
+#define VSPID6_OUT_IDX 138
+#define VSPID7_IN_IDX 139
+#define VSPID7_OUT_IDX 139
+#define I2S0I_DATA_IN0_IDX 140
+#define I2S0O_DATA_OUT0_IDX 140
+#define I2S0I_DATA_IN1_IDX 141
+#define I2S0O_DATA_OUT1_IDX 141
+#define I2S0I_DATA_IN2_IDX 142
+#define I2S0O_DATA_OUT2_IDX 142
+#define I2S0I_DATA_IN3_IDX 143
+#define I2S0O_DATA_OUT3_IDX 143
+#define I2S0I_DATA_IN4_IDX 144
+#define I2S0O_DATA_OUT4_IDX 144
+#define I2S0I_DATA_IN5_IDX 145
+#define I2S0O_DATA_OUT5_IDX 145
+#define I2S0I_DATA_IN6_IDX 146
+#define I2S0O_DATA_OUT6_IDX 146
+#define I2S0I_DATA_IN7_IDX 147
+#define I2S0O_DATA_OUT7_IDX 147
+#define I2S0I_DATA_IN8_IDX 148
+#define I2S0O_DATA_OUT8_IDX 148
+#define I2S0I_DATA_IN9_IDX 149
+#define I2S0O_DATA_OUT9_IDX 149
+#define I2S0I_DATA_IN10_IDX 150
+#define I2S0O_DATA_OUT10_IDX 150
+#define I2S0I_DATA_IN11_IDX 151
+#define I2S0O_DATA_OUT11_IDX 151
+#define I2S0I_DATA_IN12_IDX 152
+#define I2S0O_DATA_OUT12_IDX 152
+#define I2S0I_DATA_IN13_IDX 153
+#define I2S0O_DATA_OUT13_IDX 153
+#define I2S0I_DATA_IN14_IDX 154
+#define I2S0O_DATA_OUT14_IDX 154
+#define I2S0I_DATA_IN15_IDX 155
+#define I2S0O_DATA_OUT15_IDX 155
+#define ATRST_IN_IDX 156
+#define I2S0O_DATA_OUT16_IDX 156
+#define I2S0O_DATA_OUT17_IDX 157
+#define I2S0O_DATA_OUT18_IDX 158
+#define I2S0O_DATA_OUT19_IDX 159
+#define I2S0O_DATA_OUT20_IDX 160
+#define I2S0O_DATA_OUT21_IDX 161
+#define I2S0O_DATA_OUT22_IDX 162
+#define I2S0O_DATA_OUT23_IDX 163
+#define I2S1I_BCK_IN_IDX 164
+#define I2S1I_BCK_OUT_IDX 164
+#define I2S1I_WS_IN_IDX 165
+#define I2S1I_WS_OUT_IDX 165
+#define I2S1I_DATA_IN0_IDX 166
+#define I2S1O_DATA_OUT0_IDX 166
+#define I2S1I_DATA_IN1_IDX 167
+#define I2S1O_DATA_OUT1_IDX 167
+#define I2S1I_DATA_IN2_IDX 168
+#define I2S1O_DATA_OUT2_IDX 168
+#define I2S1I_DATA_IN3_IDX 169
+#define I2S1O_DATA_OUT3_IDX 169
+#define I2S1I_DATA_IN4_IDX 170
+#define I2S1O_DATA_OUT4_IDX 170
+#define I2S1I_DATA_IN5_IDX 171
+#define I2S1O_DATA_OUT5_IDX 171
+#define I2S1I_DATA_IN6_IDX 172
+#define I2S1O_DATA_OUT6_IDX 172
+#define I2S1I_DATA_IN7_IDX 173
+#define I2S1O_DATA_OUT7_IDX 173
+#define I2S1I_DATA_IN8_IDX 174
+#define I2S1O_DATA_OUT8_IDX 174
+#define I2S1I_DATA_IN9_IDX 175
+#define I2S1O_DATA_OUT9_IDX 175
+#define I2S1I_DATA_IN10_IDX 176
+#define I2S1O_DATA_OUT10_IDX 176
+#define I2S1I_DATA_IN11_IDX 177
+#define I2S1O_DATA_OUT11_IDX 177
+#define I2S1I_DATA_IN12_IDX 178
+#define I2S1O_DATA_OUT12_IDX 178
+#define I2S1I_DATA_IN13_IDX 179
+#define I2S1O_DATA_OUT13_IDX 179
+#define I2S1I_DATA_IN14_IDX 180
+#define I2S1O_DATA_OUT14_IDX 180
+#define I2S1I_DATA_IN15_IDX 181
+#define I2S1O_DATA_OUT15_IDX 181
+#define I2S1O_DATA_OUT16_IDX 182
+#define I2S1O_DATA_OUT17_IDX 183
+#define I2S1O_DATA_OUT18_IDX 184
+#define I2S1O_DATA_OUT19_IDX 185
+#define I2S1O_DATA_OUT20_IDX 186
+#define I2S1O_DATA_OUT21_IDX 187
+#define I2S1O_DATA_OUT22_IDX 188
+#define I2S1O_DATA_OUT23_IDX 189
+#define I2S0I_H_SYNC_IDX 190
+#define PWM3_OUT1H_IDX 190
+#define I2S0I_V_SYNC_IDX 191
+#define PWM3_OUT1L_IDX 191
+#define I2S0I_H_ENABLE_IDX 192
+#define PWM3_OUT2H_IDX 192
+#define I2S1I_H_SYNC_IDX 193
+#define PWM3_OUT2L_IDX 193
+#define I2S1I_V_SYNC_IDX 194
+#define PWM3_OUT3H_IDX 194
+#define I2S1I_H_ENABLE_IDX 195
+#define PWM3_OUT3L_IDX 195
+#define PWM3_OUT4H_IDX 196
+#define PWM3_OUT4L_IDX 197
+#define U2RXD_IN_IDX 198
+#define U2TXD_OUT_IDX 198
+#define U2CTS_IN_IDX 199
+#define U2RTS_OUT_IDX 199
+#define EMAC_MDC_I_IDX 200
+#define EMAC_MDC_O_IDX 200
+#define EMAC_MDI_I_IDX 201
+#define EMAC_MDO_O_IDX 201
+#define EMAC_CRS_I_IDX 202
+#define EMAC_CRS_O_IDX 202
+#define EMAC_COL_I_IDX 203
+#define EMAC_COL_O_IDX 203
+#define PCMFSYNC_IN_IDX 204
+#define BT_AUDIO0_IRQ_IDX 204
+#define PCMCLK_IN_IDX 205
+#define BT_AUDIO1_IRQ_IDX 205
+#define PCMDIN_IDX 206
+#define BT_AUDIO2_IRQ_IDX 206
+#define BLE_AUDIO0_IRQ_IDX 207
+#define BLE_AUDIO1_IRQ_IDX 208
+#define BLE_AUDIO2_IRQ_IDX 209
+#define PCMFSYNC_OUT_IDX 210
+#define PCMCLK_OUT_IDX 211
+#define PCMDOUT_IDX 212
+#define BLE_AUDIO_SYNC0_P_IDX 213
+#define BLE_AUDIO_SYNC1_P_IDX 214
+#define BLE_AUDIO_SYNC2_P_IDX 215
+#define ANT_SEL0_IDX 216
+#define ANT_SEL1_IDX 217
+#define ANT_SEL2_IDX 218
+#define ANT_SEL3_IDX 219
+#define ANT_SEL4_IDX 220
+#define ANT_SEL5_IDX 221
+#define ANT_SEL6_IDX 222
+#define ANT_SEL7_IDX 223
+#define SIG_IN_FUNC224_IDX 224
+#define SIG_IN_FUNC225_IDX 225
+#define SIG_IN_FUNC226_IDX 226
+#define SIG_IN_FUNC227_IDX 227
+#define SIG_IN_FUNC228_IDX 228
+
+#endif /* _DRIVER_GPIO_SIG_MAP_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef _DRIVER_I2C_H_\r
+#define _DRIVER_I2C_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include "esp_types.h"\r
+#include "soc/i2c_reg.h"\r
+#include "soc/soc.h"\r
+#include "soc/dport_reg.h"\r
+\r
+#define I2C_DEV(i) ((i2c_dev_t *)(REG_I2C_BASE(i)))\r
+#define I2C_APB_CLK_FREQ APB_CLK_FREQ\r
+#define I2C_COMD_REG(i2c_no, cmd_no) (I2C_COMD0_REG(i2c_no)+ (cmd_no)*4 )\r
+#define I2C_COMMAND_DONE (BIT(31))\r
+#define I2C_COMMAND_DONE_M (BIT(31))\r
+#define I2C_COMMAND_DONE_V 0x1\r
+#define I2C_COMMAND_DONE_S 31\r
+#define I2C_COMMAND_OP_CODE 0x7\r
+#define I2C_COMMAND_OP_CODE_M ((I2C_COMMAND_OP_CODE_V)<<(I2C_COMMAND_OP_CODE_S))\r
+#define I2C_COMMAND_OP_CODE_V 0x7\r
+#define I2C_COMMAND_OP_CODE_S 11\r
+#define I2C_COMMAND_ACK_VALUE (BIT(10))\r
+#define I2C_COMMAND_ACK_VALUE_M (BIT(10))\r
+#define I2C_COMMAND_ACK_VALUE_V 0x1\r
+#define I2C_COMMAND_ACK_VALUE_S 10\r
+#define I2C_COMMAND_ACK_EXP (BIT(9))\r
+#define I2C_COMMAND_ACK_EXP_M (BIT(9))\r
+#define I2C_COMMAND_ACK_EXP_V 0x1\r
+#define I2C_COMMAND_ACK_EXP_S 9\r
+#define I2C_COMMAND_ACK_EN (BIT(8))\r
+#define I2C_COMMAND_ACK_EN_M (BIT(8))\r
+#define I2C_COMMAND_ACK_EN_V 0x1\r
+#define I2C_COMMAND_ACK_EN_S 8\r
+#define I2C_COMMAND_BYTE_NUM 0xff\r
+#define I2C_COMMAND_BYTE_NUM_M 0xff\r
+#define I2C_COMMAND_BYTE_NUM_V 0xff\r
+#define I2C_COMMAND_BYTE_NUM_S 0\r
+\r
+typedef enum{\r
+ I2C_SLAVE_MODE = 0,\r
+ I2C_MASTER_MODE,\r
+}enum_i2c_mode_t;\r
+\r
+typedef enum{\r
+ I2C_CMD_RESTART = 0,\r
+ I2C_CMD_WRITE,\r
+ I2C_CMD_READ,\r
+ I2C_CMD_STOP,\r
+ I2C_CMD_END\r
+}enum_cmd_opcode_t;\r
+\r
+typedef enum{\r
+ I2C0 = 0, // 0x3ff53000\r
+ I2C1 , // 0x3ff67000\r
+ I2C_MAX\r
+} enum_i2c_port_t;\r
+\r
+typedef struct{\r
+ enum_i2c_mode_t mode;\r
+ uint8_t addr_10bit_en;\r
+ uint16_t slave_addr;\r
+ uint32_t clk_speed;\r
+}i2c_config_t;\r
+\r
+typedef struct{\r
+ uint8_t byte_num;\r
+ uint8_t ack_en;\r
+ uint8_t ack_exp;\r
+ uint8_t ack_val;\r
+ enum_cmd_opcode_t op_code;\r
+}i2c_cmd_def_t;\r
+\r
+\r
+/**\r
+ * @brief Reset I2C tx fifo, flush the data in tx fifo.\r
+ *\r
+ * @param enum_i2c_port_t i2c_no : I2C port num (I2C0 or I2C1)\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_reset_tx_fifo(enum_i2c_port_t i2c_no );\r
+\r
+/**\r
+ * @brief Fill the tx fifo with the given data bytes\r
+ *\r
+ * @param enum_i2c_port_t i2c_no : I2C port num (I2C0 or I2C1)\r
+ * @param uint8_t *data : pointer to the data buffer\r
+ * @param uint8_t len : data length of the data\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_tx_fifo_push(enum_i2c_port_t i2c_no,uint8_t *data , uint8_t len);\r
+\r
+/**\r
+ * @brief Reset I2C rx fifo, flush the data in rx fifo.\r
+ *\r
+ * @param enum_i2c_port_t i2c_no : I2C port num (I2C0 or I2C1)\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_reset_rx_fifo(enum_i2c_port_t i2c_no);\r
+\r
+/**\r
+ * @brief Fill the tx fifo with the given data bytes\r
+ *\r
+ * @param enum_i2c_port_t i2c_no : I2C port num (I2C0 or I2C1)\r
+ * @param uint8_t cmd_idx : i2c command index(at most 16 commands one time)\r
+ * @param i2c_cmd_def_t* cmd : command definition.\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_config_cmd(enum_i2c_port_t i2c_no,uint8_t cmd_idx, i2c_cmd_def_t* cmd);\r
+\r
+/**\r
+ * @brief Start sending data to i2c bus.The data is defined in the command registers.Stop when there is a "STOP" command\r
+ *\r
+ * @param enum_i2c_port_t i2c_no : I2C port num (I2C0 or I2C1)\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_start(enum_i2c_port_t i2c_no);\r
+\r
+/**\r
+ * @brief Set and initialize i2c params\r
+ *\r
+ * @param enum_i2c_port_t i2c_no : I2C port num (I2C0 or I2C1)\r
+ * @param i2c_config_t* i2c_conf : i2c setting param struct\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_init( enum_i2c_port_t i2c_no, i2c_config_t* i2c_conf);\r
+\r
+/**\r
+ * @brief Set and initialize i2c interruption handler\r
+ *\r
+ * @param uint8_t cpu_num : CPU number (PRO_CPU_NUM or APP_CPU_NUM)\r
+ * @param enum_i2c_port_t i2c_no : I2C port num (I2C0 or I2C1)\r
+ * @param uint8_t i2c_intr_num : i2c interrupt number, set this value according to interrupt cpu using table, Please see the core-isa.h\r
+ * @param void (* fn)(void* ) : i2c interrupt handler\r
+ * @param void * arg : param pointer of i2c interrupt handler\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_intr_register(uint8_t cpu_num,enum_i2c_port_t i2c_no,uint8_t i2c_intr_num,void (* fn)(void* ),void * arg);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*_DRIVER_I2C_H_*/\r
--- /dev/null
+#ifndef __I2C_MASTER_H__\r
+#define __I2C_MASTER_H__\r
+\r
+#include <stdio.h>\r
+#include "driver/gpio.h"\r
+#include "esp_types.h"\r
+#include "rom/ets_sys.h"\r
+\r
+#if 0\r
+#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_MTMS_U\r
+#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_MTDO_U\r
+#define I2C_MASTER_SDA_GPIO 14\r
+#define I2C_MASTER_SCL_GPIO 15\r
+#define I2C_MASTER_SDA_FUNC FUNC_MTMS_GPIO14\r
+#define I2C_MASTER_SCL_FUNC FUNC_MTDO_GPIO15\r
+#endif\r
+\r
+#if 0\r
+#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO26_U\r
+#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO27_U\r
+#define I2C_MASTER_SDA_GPIO 26\r
+#define I2C_MASTER_SDA_PIN GPIO_Pin_26\r
+\r
+#define I2C_MASTER_SCL_PIN GPIO_Pin_27\r
+#define I2C_MASTER_SCL_GPIO 27\r
+#define I2C_MASTER_SDA_FUNC FUNC_GPIO26_GPIO26\r
+#define I2C_MASTER_SCL_FUNC FUNC_GPIO27_GPIO27\r
+#endif\r
+\r
+#if 1\r
+\r
+#define I2C_MASTER_SDA_GPIO 21\r
+#define I2C_MASTER_SDA_PIN GPIO_SEL_21\r
+\r
+#define I2C_MASTER_SCL_PIN GPIO_SEL_19\r
+#define I2C_MASTER_SCL_GPIO 19\r
+#endif\r
+\r
+#if 0\r
+#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO23_U\r
+#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO5_U\r
+#define I2C_MASTER_SDA_GPIO 23\r
+#define I2C_MASTER_SDA_PIN GPIO_Pin_23\r
+\r
+#define I2C_MASTER_SCL_PIN GPIO_Pin_5\r
+#define I2C_MASTER_SCL_GPIO 5\r
+#define I2C_MASTER_SDA_FUNC FUNC_GPIO23_GPIO23\r
+#define I2C_MASTER_SCL_FUNC FUNC_GPIO5_GPIO5\r
+#endif\r
+\r
+#define I2C_MASTER_SDA_HIGH_SCL_HIGH() \\r
+ gpio_set_level(I2C_MASTER_SDA_GPIO,1);\\r
+ gpio_set_level(I2C_MASTER_SCL_GPIO,1);\r
+\r
+#define I2C_MASTER_SDA_HIGH_SCL_LOW() \\r
+ gpio_set_level(I2C_MASTER_SDA_GPIO,1);\\r
+ gpio_set_level(I2C_MASTER_SCL_GPIO,0);\r
+\r
+#define I2C_MASTER_SDA_LOW_SCL_HIGH() \\r
+ gpio_set_level(I2C_MASTER_SDA_GPIO,0);\\r
+ gpio_set_level(I2C_MASTER_SCL_GPIO,1);\r
+\r
+#define I2C_MASTER_SDA_LOW_SCL_LOW() \\r
+ gpio_set_level(I2C_MASTER_SDA_GPIO,0);\\r
+ gpio_set_level(I2C_MASTER_SCL_GPIO,0);\r
+\r
+/** \defgroup Driver_APIs Driver APIs\r
+ * @brief Driver APIs\r
+ */\r
+\r
+/** @addtogroup Driver_APIs\r
+ * @{\r
+ */\r
+\r
+/** \defgroup I2C_Driver_APIs I2C_MASTER Driver APIs\r
+ * @brief UART driver APIs\r
+ */\r
+\r
+/** @addtogroup I2C_MASTER_Driver_APIs\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.\r
+ *\r
+ * @param null\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_gpio_init(void);\r
+\r
+/**\r
+ * @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.\r
+ *\r
+ * @param initilize I2C bus to enable i2c operations.\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_init(void);\r
+\r
+#define i2c_master_wait ets_delay_us\r
+\r
+\r
+/**\r
+ * @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.\r
+ *\r
+ * @param set i2c to stop sending state.\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_stop(void);\r
+\r
+/**\r
+ * @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.\r
+ *\r
+ * @param set i2c to start sending state.\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_start(void);\r
+\r
+/**\r
+ * @brief i2c_master_gpio_init,config SDA and SCL gpio to open-drain output mode.\r
+ *\r
+ * @param set ack to i2c bus as level value.\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_setAck(uint8_t level);\r
+\r
+/**\r
+ * @brief confirm if peer send ack.\r
+ *\r
+ * @param null\r
+ *\r
+ * @return null\r
+ */\r
+uint8_t i2c_master_getAck(void);\r
+\r
+/**\r
+ * @brief read Byte from i2c bus.\r
+ *\r
+ * @param null\r
+ *\r
+ * @return the byte which read from i2c bus.\r
+ */\r
+uint8_t i2c_master_readByte(void);\r
+\r
+/**\r
+ * @brief write wrdata value(one byte) into i2c.\r
+ *\r
+ * @param uint8_t wrdata:write value\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_writeByte(uint8_t wrdata);\r
+\r
+/**\r
+ * @brief i2c_master_checkAck.\r
+ *\r
+ * @param null\r
+ *\r
+ * @return the result of check ack\r
+ */\r
+bool i2c_master_checkAck(void);\r
+\r
+/**\r
+ * @brief i2c master send Ack.\r
+ *\r
+ * @param null\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_send_ack(void);\r
+\r
+/**\r
+ * @brief i2c master send Nack.\r
+ *\r
+ * @param null\r
+ *\r
+ * @return null\r
+ */\r
+void i2c_master_send_nack(void);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif\r
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+\r
+#ifndef _DRIVER_II2C_STRUCT_H_\r
+#define _DRIVER_II2C_STRUCT_H_\r
+\r
+\r
+typedef struct I2C_DEV{\r
+ union {\r
+ struct {\r
+ unsigned int scl_low_period: 14;\r
+ unsigned int reserved14: 18;\r
+ } fld;\r
+ uint32_t val;\r
+ } SCL_LOW_PERIOD;\r
+ union {\r
+ struct {\r
+ unsigned int sda_force_out: 1;\r
+ unsigned int scl_force_out: 1;\r
+ unsigned int sample_scl_level: 1;\r
+ unsigned int reserved3: 1;\r
+ unsigned int ms_mode: 1;\r
+ unsigned int trans_start: 1;\r
+ unsigned int tx_lsb_first: 1;\r
+ unsigned int rx_lsb_first: 1;\r
+ unsigned int clk_en: 1;\r
+ unsigned int reserved9: 23;\r
+ } fld;\r
+ uint32_t val;\r
+ } CTR;\r
+ union {\r
+ struct {\r
+ unsigned int ack_rec: 1;\r
+ unsigned int slave_rw: 1;\r
+ unsigned int time_out: 1;\r
+ unsigned int arb_lost: 1;\r
+ unsigned int bus_busy: 1;\r
+ unsigned int slave_addressed: 1;\r
+ unsigned int byte_trans: 1;\r
+ unsigned int reserved7: 1;\r
+ unsigned int rxfifo_cnt: 6;\r
+ unsigned int reserved14: 4;\r
+ unsigned int txfifo_cnt: 6;\r
+ unsigned int scl_main_state_last: 3;\r
+ unsigned int reserved27: 1;\r
+ unsigned int scl_state_last: 3;\r
+ unsigned int reserved31: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } SR;\r
+ union {\r
+ struct {\r
+ unsigned int time_out_reg: 20;\r
+ unsigned int reserved20: 12;\r
+ } fld;\r
+ uint32_t val;\r
+ } TO;\r
+ union {\r
+ struct {\r
+ unsigned int slave_addr: 15;\r
+ unsigned int reserved15: 16;\r
+ unsigned int addr_10bit_en: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } SLAVE_ADDR;\r
+ union {\r
+ struct {\r
+ unsigned int rxfifo_start_addr: 5;\r
+ unsigned int rxfifo_end_addr: 5;\r
+ unsigned int txfifo_start_addr: 5;\r
+ unsigned int txfifo_end_addr: 5;\r
+ unsigned int reserved20: 12;\r
+ } fld;\r
+ uint32_t val;\r
+ } RXFIFO_ST;\r
+ union {\r
+ struct {\r
+ unsigned int rxfifo_full_thrhd: 5;\r
+ unsigned int txfifo_empty_thrhd: 5;\r
+ unsigned int nonfifo_en: 1;\r
+ unsigned int fifo_addr_cfg_en: 1;\r
+ unsigned int rx_fifo_rst: 1;\r
+ unsigned int tx_fifo_rst: 1;\r
+ unsigned int nonfifo_rx_thres: 6;\r
+ unsigned int nonfifo_tx_thres: 6;\r
+ unsigned int reserved26: 6;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_FIFO_CONF;\r
+ union {\r
+ struct {\r
+ unsigned int fifo_data: 8;\r
+ unsigned int reserved8: 24;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_DATA;\r
+ union {\r
+ struct {\r
+ unsigned int rxfifo_full_int_raw: 1;\r
+ unsigned int txfifo_empty_int_raw: 1;\r
+ unsigned int rxfifo_ovf_int_raw: 1;\r
+ unsigned int end_detect_int_raw: 1;\r
+ unsigned int slave_tran_comp_int_raw: 1;\r
+ unsigned int arbitration_lost_int_raw: 1;\r
+ unsigned int master_tran_comp_int_raw: 1;\r
+ unsigned int trans_complete_int_raw: 1;\r
+ unsigned int time_out_int_raw: 1;\r
+ unsigned int trans_start_int_raw: 1;\r
+ unsigned int ack_err_int_raw: 1;\r
+ unsigned int rx_rec_full_int_raw: 1;\r
+ unsigned int tx_send_empty_int_raw: 1;\r
+ unsigned int reserved13: 19;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_INT_RAW;\r
+ union {\r
+ struct {\r
+ unsigned int rxfifo_full_int_clr: 1;\r
+ unsigned int txfifo_empty_int_clr: 1;\r
+ unsigned int rxfifo_ovf_int_clr: 1;\r
+ unsigned int end_detect_int_clr: 1;\r
+ unsigned int slave_tran_comp_int_clr: 1;\r
+ unsigned int arbitration_lost_int_clr: 1;\r
+ unsigned int master_tran_comp_int_clr: 1;\r
+ unsigned int trans_complete_int_clr: 1;\r
+ unsigned int time_out_int_clr: 1;\r
+ unsigned int trans_start_int_clr: 1;\r
+ unsigned int ack_err_int_clr: 1;\r
+ unsigned int rx_rec_full_int_clr: 1;\r
+ unsigned int tx_send_empty_int_clr: 1;\r
+ unsigned int reserved13: 19;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_INT_CLR;\r
+ union {\r
+ struct {\r
+ unsigned int rxfifo_full_int_ena: 1;\r
+ unsigned int txfifo_empty_int_ena: 1;\r
+ unsigned int rxfifo_ovf_int_ena: 1;\r
+ unsigned int end_detect_int_ena: 1;\r
+ unsigned int slave_tran_comp_int_ena: 1;\r
+ unsigned int arbitration_lost_int_ena: 1;\r
+ unsigned int master_tran_comp_int_ena: 1;\r
+ unsigned int trans_complete_int_ena: 1;\r
+ unsigned int time_out_int_ena: 1;\r
+ unsigned int trans_start_int_ena: 1;\r
+ unsigned int ack_err_int_ena: 1;\r
+ unsigned int rx_rec_full_int_ena: 1;\r
+ unsigned int tx_send_empty_int_ena: 1;\r
+ unsigned int reserved13: 19;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_INT_ENA;\r
+ union {\r
+ struct {\r
+ unsigned int rxfifo_full_int_st: 1;\r
+ unsigned int txfifo_empty_int_st: 1;\r
+ unsigned int rxfifo_ovf_int_st: 1;\r
+ unsigned int end_detect_int_st: 1;\r
+ unsigned int slave_tran_comp_int_st: 1;\r
+ unsigned int arbitration_lost_int_st: 1;\r
+ unsigned int master_tran_comp_int_st: 1;\r
+ unsigned int trans_complete_int_st: 1;\r
+ unsigned int time_out_int_st: 1;\r
+ unsigned int trans_start_int_st: 1;\r
+ unsigned int ack_err_int_st: 1;\r
+ unsigned int rx_rec_full_int_st: 1;\r
+ unsigned int tx_send_empty_int_st: 1;\r
+ unsigned int reserved13: 19;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_INT_STATUS;\r
+ union {\r
+ struct {\r
+ unsigned int sda_hold_time: 10;\r
+ unsigned int reserved10: 22;\r
+ } fld;\r
+ uint32_t val;\r
+ } SDA_HOLD;\r
+ union {\r
+ struct {\r
+ unsigned int sda_sample_time: 10;\r
+ unsigned int reserved10: 22;\r
+ } fld;\r
+ uint32_t val;\r
+ } SDA_SAMPLE;\r
+ union {\r
+ struct {\r
+ unsigned int scl_high_period: 14;\r
+ unsigned int reserved14: 18;\r
+ } fld;\r
+ uint32_t val;\r
+ } SCL_HIGH_PERIOD;\r
+ uint32_t reserved_3c;\r
+ union {\r
+ struct {\r
+ unsigned int scl_start_hold_time: 10;\r
+ unsigned int reserved10: 22;\r
+ } fld;\r
+ uint32_t val;\r
+ } SCL_START_HOLD;\r
+ union {\r
+ struct {\r
+ unsigned int scl_rstart_setup_time: 10;\r
+ unsigned int reserved10: 22;\r
+ } fld;\r
+ uint32_t val;\r
+ } SCL_RSTART_SETUP;\r
+ union {\r
+ struct {\r
+ unsigned int scl_stop_hold_time: 14;\r
+ unsigned int reserved14: 18;\r
+ } fld;\r
+ uint32_t val;\r
+ } SCL_STOP_HOLD;\r
+ union {\r
+ struct {\r
+ unsigned int scl_stop_setup_time: 10;\r
+ unsigned int reserved10: 22;\r
+ } fld;\r
+ uint32_t val;\r
+ } SCL_STOP_SETUP;\r
+ union {\r
+ struct {\r
+ unsigned int scl_filter_thres: 3;\r
+ unsigned int scl_filter_en: 1;\r
+ unsigned int reserved4: 28;\r
+ } fld;\r
+ uint32_t val;\r
+ } SCL_FILTER_CFG;\r
+ union {\r
+ struct {\r
+ unsigned int sda_filter_thres: 3;\r
+ unsigned int sda_filter_en: 1;\r
+ unsigned int reserved4: 28;\r
+ } fld;\r
+ uint32_t val;\r
+ } SDA_FILTER_CFG;\r
+ union {\r
+ struct {\r
+ //unsigned int command: 14;\r
+ unsigned int command_byte_num: 8;\r
+ unsigned int command_ack_en: 1;\r
+ unsigned int command_ack_exp: 1;\r
+ unsigned int command_ack_val: 1;\r
+ unsigned int command_op_code: 3;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD[16];\r
+#if 0\r
+ union {\r
+ struct {\r
+ unsigned int command1: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command1_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD1;\r
+ union {\r
+ struct {\r
+ unsigned int command2: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command2_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD2;\r
+ union {\r
+ struct {\r
+ unsigned int command3: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command3_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD3;\r
+ union {\r
+ struct {\r
+ unsigned int command4: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command4_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD4;\r
+ union {\r
+ struct {\r
+ unsigned int command5: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command5_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD5;\r
+ union {\r
+ struct {\r
+ unsigned int command6: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command6_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD6;\r
+ union {\r
+ struct {\r
+ unsigned int command7: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command7_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD7;\r
+ union {\r
+ struct {\r
+ unsigned int command8: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command8_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD8;\r
+ union {\r
+ struct {\r
+ unsigned int command9: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command9_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD9;\r
+ union {\r
+ struct {\r
+ unsigned int command10: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command10_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD10;\r
+ union {\r
+ struct {\r
+ unsigned int command11: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command11_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD11;\r
+ union {\r
+ struct {\r
+ unsigned int command12: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command12_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD12;\r
+ union {\r
+ struct {\r
+ unsigned int command13: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command13_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD13;\r
+ union {\r
+ struct {\r
+ unsigned int command14: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command14_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD14;\r
+ union {\r
+ struct {\r
+ unsigned int command15: 14;\r
+ unsigned int reserved14: 17;\r
+ unsigned int command15_done: 1;\r
+ } fld;\r
+ uint32_t val;\r
+ } I2C_COMD15;\r
+#endif\r
+ uint32_t reserved_98;\r
+ uint32_t reserved_9c;\r
+ uint32_t reserved_a0;\r
+ uint32_t reserved_a4;\r
+ uint32_t reserved_a8;\r
+ uint32_t reserved_ac;\r
+ uint32_t reserved_b0;\r
+ uint32_t reserved_b4;\r
+ uint32_t reserved_b8;\r
+ uint32_t reserved_bc;\r
+ uint32_t reserved_c0;\r
+ uint32_t reserved_c4;\r
+ uint32_t reserved_c8;\r
+ uint32_t reserved_cc;\r
+ uint32_t reserved_d0;\r
+ uint32_t reserved_d4;\r
+ uint32_t reserved_d8;\r
+ uint32_t reserved_dc;\r
+ uint32_t reserved_e0;\r
+ uint32_t reserved_e4;\r
+ uint32_t reserved_e8;\r
+ uint32_t reserved_ec;\r
+ uint32_t reserved_f0;\r
+ uint32_t reserved_f4;\r
+ //struct {\r
+ // uint32_t val;\r
+ //}I2C_DATE;\r
+ uint32_t reserved_fc;\r
+ //struct {\r
+ // uint32_t val;\r
+ //}I2C_FIFO_START_ADDR;\r
+}I2C_TypeDef;\r
+\r
+\r
+#endif\r
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef _DRIVER_I2S_H_
+#define _DRIVER_I2S_H_
+#include "soc/dport_reg.h"
+#include "soc/i2s_reg.h"
+#include <stdint.h>
+#include "dma.h"
+#include "soc/soc.h"
+#include "esp_err.h"
+
+#define ETS_I2S0_INUM 17
+#define ETS_I2S1_INUM 17
+
+#define ESP_I2S1_INTR_ATTACH(func, arg) \
+ xt_set_interrupt_handler(ETS_I2S1_INUM, (func), (void *)(arg))
+
+
+//*****************************************************************************
+//
+// Make sure all of the definitions in this header have a C binding.
+//
+//*****************************************************************************
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup Driver_APIs Driver APIs
+ * @brief Driver APIs
+ */
+
+/** @addtogroup Driver_APIs
+ * @{
+ */
+
+/** \defgroup I2S_Driver_APIs I2S Driver APIs
+ * @brief I2S driver APIs
+ */
+
+/** @addtogroup I2S_Driver_APIs
+ * @{
+ */
+
+// ena:1 enable audio pll;
+// 0 disable audio pll;
+// freq = (xtal * (sdm2 + 4))/((o_div+2)*2)
+// xtal is 40M/26M
+// (xtal * (sdm2 + 4)):240 ~ 600MHz
+// o_div : 0 ~ 31
+void rtc_plla_ena(uint8_t ena, uint32_t sdm2, uint32_t o_div);
+
+
+/**
+ * @brief Two I2S module.I2S0 has support pdm.
+ *
+ */
+typedef enum {
+ I2S_NUM_I2S0 = 0x0,
+ I2S_NUM_I2S1 = 0x1,
+ I2S_NUM_MAX = I2S_NUM_I2S1,
+} i2s_num_t;
+
+/**
+ * @brief I2S module working mode.
+ *
+ */
+typedef enum {
+ I2S_MODE_MASTER_TX = 1,
+ I2S_MODE_MASTER_RX = 2,
+ I2S_MODE_SLAVE_TX = 3,
+ I2S_MODE_SLAVE_RX = 4,
+} i2s_mode_t;
+
+/**
+ * @brief I2S bit width per sample.
+ *
+ */
+typedef enum {
+ I2S_BITS_PER_SAMPLE_8BIT = 8,
+ I2S_BITS_PER_SAMPLE_16BIT = 16,
+ I2S_BITS_PER_SAMPLE_24BIT = 24,
+ I2S_BITS_PER_SAMPLE_32BIT = 32,
+} i2s_sample_bits_t;
+
+/**
+ * @brief I2S audio data formats.
+ *
+ */
+typedef enum {
+ I2S_STD_FORMAT_I2S,
+ I2S_STD_FORMAT_MSB,
+ I2S_STD_FORMAT_LSB,
+ I2S_STD_FORMAT_PCM_SHORT,
+ I2S_STD_FORMAT_PCM_LONG,
+} i2s_std_format_t;
+
+/**
+ * @brief I2S data port interface type
+ */
+typedef enum {
+ I2S_IFACE_TYPE_DMA,
+ I2S_IFACE_TYPE_CPU,
+} i2s_interface_t;
+
+
+/**
+ * @brief I2S channel format type
+ */
+typedef enum {
+ I2S_CHANNEL_FMT_RIGHT_LEFT,
+ I2S_CHANNEL_FMT_ALL_RIGHT,
+ I2S_CHANNEL_FMT_ALL_LEFT,
+ I2S_CHANNEL_FMT_ONLY_RIGHT,
+ I2S_CHANNEL_FMT_ONLY_LEFT,
+} i2s_channel_fmt_t;
+
+/**
+ * @brief I2S audio sample rate per second, measured in Hz.
+ *
+ */
+typedef enum {
+ I2S_SAMPLE_RATE_96K = 96000,
+ I2S_SAMPLE_RATE_48K = 48000,
+ I2S_SAMPLE_RATE_44K = 44100,
+ I2S_SAMPLE_RATE_32K = 32000,
+ I2S_SAMPLE_RATE_22K = 22050,
+ I2S_SAMPLE_RATE_16K = 16000,
+ I2S_SAMPLE_RATE_11K = 11025,
+ I2S_SAMPLE_RATE_8K = 8000,
+} i2s_sample_rate_t;
+
+/**
+ * @brief PDM sample rate ratio, measured in Hz.
+ *
+ */
+typedef enum {
+ PDM_SAMPLE_RATE_RATIO_64,
+ PDM_SAMPLE_RATE_RATIO_128,
+} pdm_sample_rate_ratio_t;
+
+/**
+ * @brief PDM PCM convter enable/disable.
+ *
+ */
+typedef enum {
+ PDM_PCM_CONV_ENABLE,
+ PDM_PCM_CONV_DISABLE,
+} pdm_pcm_conv_t;
+
+/**
+ * @brief I2s module work type.
+ *
+ */
+typedef enum {
+ I2S_MODULE_WORK_TYPE_I2S,
+ I2S_MODULE_WORK_TYPE_PDM,
+} i2s_module_work_type_t;
+
+
+// @brief I2S interrupt source defined.
+typedef enum {
+ I2S_INT_SRC_ONE_BUF_SEND_DONE = I2S_OUT_EOF_INT_ENA, //BIT(12) One package buffer has been sent.
+ I2S_INT_SRC_ONE_BUF_RECV_DONE = I2S_IN_SUC_EOF_INT_ENA, //BIT(9) Received one package buffer
+
+ I2S_INT_SRC_TX_EMPTY = I2S_TX_REMPTY_INT_ENA, //BIT(5) Tx buffer is empty
+ I2S_INT_SRC_RX_FULL = I2S_RX_WFULL_INT_ENA, //BIT(2) Rx buffer is full
+ I2S_INT_SRC_TX_HALF_EMPTY = I2S_TX_PUT_DATA_INT_ENA, //BIT(1) Tx buffer is half empty
+ I2S_INT_SRC_RX_HALF_FULL = I2S_RX_TAKE_DATA_INT_ENA, //BIT(0) Rx buffer is half full
+} i2s_int_src_t;
+
+/**
+ * @brief I2S attribute
+ */
+typedef struct {
+ i2s_module_work_type_t type;
+ i2s_mode_t mode;
+ i2s_sample_rate_t rate;
+ i2s_sample_bits_t bits;
+ i2s_std_format_t std;
+ i2s_interface_t iface;
+ i2s_channel_fmt_t channel;
+ pdm_sample_rate_ratio_t ratio;
+ pdm_pcm_conv_t conv;
+} i2s_module_info_t;
+
+/**
+ * @brief I2S attribute
+ */
+typedef struct {
+ i2s_module_info_t tx_mode;
+ i2s_module_info_t rx_mode;
+} i2s_attr_t;
+
+// I2S DMA attribite
+typedef struct {
+ uint32_t mode;
+ uint32_t buf_size;
+ ping_pong_buf_t *buf;
+} i2s_dma_attr_t;
+
+
+/**
+ * @brief Initialize I2s with a given module.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] pAttr Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @return None
+ *
+ */
+void i2s_init(i2s_num_t i2sNum, i2s_attr_t *pAttr);
+
+/**
+ * @brief Reset I2s with a given module.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @return None
+ *
+ */
+void i2s_reset(i2s_num_t i2sNum);
+
+/**
+ * @brief Start I2s module
+ *
+ * @param[in] type Indicates I2s module which mode will be working.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] mode Indicates I2S working mode.
+ *
+ * @return None
+ *
+ */
+void i2s_start(i2s_module_work_type_t type, i2s_num_t i2sNum, i2s_mode_t mode);
+
+/**
+ * @brief Stop I2s module.
+ *
+ * @param[in] type Indicates I2s module which mode will be stop.
+ *
+ * @param[in] i2sNum Number of i2s module.
+ *
+ * @param[in] mode Indicates I2S working mode.
+ *
+ * @return None
+ *
+ */
+void i2s_stop(i2s_module_work_type_t type, i2s_num_t i2sNum, i2s_mode_t mode);
+
+/**
+ * @brief Set i2s module clock.
+ *
+ * @param[in] rate bit clock.
+ *
+ * @param[in] bits bit length.
+ *
+ * @return None
+ *
+ */
+void i2s_clk_set(int rate, int bits);
+
+/**
+ * @brief Enable I2s DMA mode.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] mode Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @return None
+ *
+ */
+void i2s_dma_enable(i2s_num_t i2sNum, i2s_mode_t mode);
+
+/**
+ * @brief Disable I2s DMA mode.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] mode Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @return None
+ *
+ */
+void i2s_dma_disable(i2s_num_t i2sNum, i2s_mode_t mode);
+
+/**
+ * @brief Get ping buffer address.
+ *
+ * @param[in] obj Number of i2s module
+ *
+ * @return None
+ *
+ */
+uint32_t* i2s_dma_ping_buf_get(i2s_dma_attr_t *obj);
+
+/**
+ * @brief Get pong buffer address.
+ *
+ * @param[in] obj Number of i2s module
+ *
+ * @param[in] pAttr Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @return None
+ *
+ */
+uint32_t* i2s_dma_pong_buf_get(i2s_dma_attr_t *obj);
+
+/**
+ * @brief Get without working ping-pong buffer address.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] obj Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @return None
+ *
+ */
+uint32_t* i2s_dma_status_get(i2s_num_t i2sNum, i2s_dma_attr_t *obj);
+
+/**
+ * @brief Set the Ping-Pong buffer to the destination
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] obj Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @return None
+ *
+ */
+void i2s_dma_dest_add_set(i2s_num_t i2sNum, i2s_dma_attr_t *obj);
+
+/**
+ * @brief Initialize DMA and create a I2S DMA instance.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] obj Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @param[in] isr Pointer to a function that will be called
+ *
+ * @return -1:indicates parameter error, -2: DMA buffer init failure, others indicates success.
+ *
+ */
+int i2s_dma_init(i2s_num_t i2sNum, i2s_dma_attr_t* obj, void *isr);
+
+/**
+ * @brief Destroy the I2S DMA instance.
+ *
+ * @param[in] obj Pointer to a struct i2s_attr_t that indicates I2S working attribution.
+ *
+ * @return ESP_FAIL:indicates parameter error, ESP_OK :indicates success.
+ *
+ */
+esp_err_t i2s_dma_uninit(i2s_dma_attr_t *obj);
+
+/**
+ * @brief Enable the I2s module interrupt source.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] intSrc Indicates which interrupt source to be enable.
+ *
+ * @return None
+ *
+ */
+void i2s_int_enable(i2s_num_t i2sNum, i2s_int_src_t intSrc);
+
+/**
+ * @brief Disable the I2s module interrupt source.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] intSrc Indicates which interrupt source to be disable.
+ *
+ * @return None
+ *
+ */
+void i2s_int_disable(i2s_num_t i2sNum, i2s_int_src_t intSrc);
+
+/**
+ * @brief Clear the I2s module interrupt source.
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @param[in] intSrc Indicates which interrupt source to be clear.
+ *
+ * @return None
+ *
+ */
+void i2s_int_clear(i2s_num_t i2sNum, i2s_int_src_t intSrc);
+
+/**
+ * @brief Get the I2s module interrupt source
+ *
+ * @param[in] i2sNum Number of i2s module
+ *
+ * @return None
+ *
+ */
+uint32_t i2s_int_status_get(i2s_num_t i2sNum);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2S_H__
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_LEDC_PWM_H_
+#define _DRIVER_LEDC_PWM_H_
+
+#include "soc/soc.h"
+#include "soc/ledc_reg.h"
+#include "driver/gpio.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*--------------------------------------------------
+ HSCHX_LEDC_PWM
+---------------------------------------------------*/
+#define LEDC_HSCHX_CONF0_REG(CHANNEL) (LEDC_HSCH0_CONF0_REG+0X14*(CHANNEL))
+#define LEDC_HSCHX_HPOINT_REG(CHANNEL) (LEDC_HSCH0_HPOINT_REG+0X14*(CHANNEL))
+#define LEDC_HSCHX_DUTY_REG(CHANNEL) (LEDC_HSCH0_DUTY_REG+0X14*(CHANNEL))
+#define LEDC_HSCHX_CONF1_REG(CHANNEL) (LEDC_HSCH0_CONF1_REG+0X14*(CHANNEL))
+#define LEDC_HSCHX_DUTY_R_REG(CHANNEL) (LEDC_HSCH0_DUTY_R_REG+0X14*(CHANNEL))
+/*-------------------------------------------------
+ LSCHX_LEDC_PWM
+--------------------------------------------------*/
+#define LEDC_LSCHX_CONF0_REG(CHANNEL) (LEDC_LSCH0_CONF0_REG+0X14*(CHANNEL))
+#define LEDC_LSCHX_HPOINT_REG(CHANNEL) (LEDC_LSCH0_HPOINT_REG+0X14*(CHANNEL))
+#define LEDC_LSCHX_DUTY_REG(CHANNEL) (LEDC_LSCH0_DUTY_REG+0X14*(CHANNEL))
+#define LEDC_LSCHX_CONF1_REG(CHANNEL) (LEDC_LSCH0_CONF1_REG+0X14*(CHANNEL))
+#define LEDC_LSCHX_DUTY_R_REG(CHANNEL) (LEDC_LSCH0_DUTY_R_REG+0X14*(CHANNEL))
+
+/*---------------------------------------------------
+ HTIMERX_LEDC_PWM
+---------------------------------------------------*/
+#define LEDC_HSTIMERX_CONF_REG(TIME) (LEDC_HSTIMER0_CONF_REG+0X08*(TIME))
+#define LEDC_HSTIMERX_VALUE_REG(TIME) (LEDC_HSTIMER0_VALUE_REG+0X08*(TIME))
+/*----------------------------------------------
+ LTIMERX_LEDC_PWM
+-----------------------------------------------*/
+#define LEDC_LSTIMERX_CONF_REG(TIME) (LEDC_LSTIMER0_CONF_REG+0X08*(TIME))
+#define LEDC_LSTIMERX_VALUE_REG(TIME) (LEDC_LSTIMER0_VALUE_REG+0X08*(TIME))
+
+enum ledc_pwm_mode{
+ LEDC_HIGH_SPEED_MODE=0, /**< Ledc high speed mode */
+ LEDC_LOW_SPEED_MODE, /**< Ledc low speed mode */
+};
+enum ledc_pwm_intr_type{
+ LEDC_INTR_DISABLE=0,/**< Disable ledc interrupt */
+ LEDC_INTR_CHANGE_END, /**< Enable ledc interrupt */
+};
+enum ledc_pwm_increase_direction{
+ LEDC_DIR_DECREASE=0,/**<ledc change decrease direction */
+ LEDC_DIR_INCREASE=1,/**<ledc change increase direction */
+};
+enum ledc_timer_source{
+ LEDC_TIMER0=0,/**<ledc source time TIME0 */
+ LEDC_TIMER1, /**<ledc source time TIME1 */
+ LEDC_TIMER2, /**<ledc source time TIME2 */
+ LEDC_TIMER3, /**<ledc source time TIME3 */
+};
+enum ledc_pwm_channel{
+ LEDC_PWM_CHANNEL0=0,/**<ledc channel 0 */
+ LEDC_PWM_CHANNEL1, /**<ledc channel 1 */
+ LEDC_PWM_CHANNEL2, /**<ledc channel 2 */
+ LEDC_PWM_CHANNEL3, /**<ledc channel 3 */
+ LEDC_PWM_CHANNEL4, /**<ledc channel 4 */
+ LEDC_PWM_CHANNEL5, /**<ledc channel 5 */
+ LEDC_PWM_CHANNEL6, /**<ledc channel 6 */
+ LEDC_PWM_CHANNEL7, /**<ledc channel 7 */
+};
+enum ledc_pwm_duty_depth{
+ LEDC_PWM_DUTY_DEPTH_10_BIT=10, /**<ledc pwm depth 10Bit */
+ LEDC_PWM_DUTY_DEPTH_11_BIT=11, /**<ledc pwm depth 11Bit */
+ LEDC_PWM_DUTY_DEPTH_12_BIT=12, /**<ledc pwm depth 12Bit */
+ LEDC_PWM_DUTY_DEPTH_13_BIT=13, /**<ledc pwm depth 13Bit */
+ LEDC_PWM_DUTY_DEPTH_14_BIT=14, /**<ledc pwm depth 14Bit */
+ LEDC_PWM_DUTY_DEPTH_15_BIT=15, /**<ledc pwm depth 15Bit */
+};
+typedef struct ledc_event_message{
+ enum ledc_pwm_mode mode;
+ enum ledc_pwm_channel channel;
+}ledc_event_msg_t;
+
+typedef void (*ledc_event_callback)(ledc_event_msg_t ledc_mes);
+
+typedef struct ledc_pwm_channel_config{
+ gpio_num_t gpio_num;
+ enum ledc_pwm_channel channel;
+ enum ledc_pwm_intr_type intr_enable;
+ /*if selet same time,the fre and the ledc_depth must be same*/
+ enum ledc_timer_source time;
+ uint32_t fre_hz;
+ uint16_t duty;
+ enum ledc_pwm_duty_depth ledc_pre_depth;
+}ledc_channel_config_t;
+
+/**
+ * @brief ledc common configuration
+ *
+ * User this Function,config ledc the channel output gpio_num,interrupt,source time,frequench(Hz),start duty,ledc depth
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] ledc_channel_config_t ledc_channel_config_t.gpio_num : the ledc output gpio_num,if you want to use gpio16,
+ * ledc_channel_config_t.gpio_num=GPIO_NUM_16
+ *
+ * ledc_channel_config_t.channel : current configuration channel
+ * ledc_channel_config_t.intr_enable : config interrupe ,Gradient interrupt enable or Gradient interrupt disable
+ * ledc_channel_config_t.time : select the time of channel, when different channel ,select same time ,their
+ * fre_hz and ledc_pre_depth must be same
+ * ledc_channel_config_t.fre_hz : ledc channel frequech(Hz),when different channel ,select same time ,their
+ * fre_hz and ledc_pre_depth must be same
+ * ledc_channel_config_t.duty : ledc channel duty,if the ledc_pre_depth = 10,the duty range is [0,2**10],
+ * ledc_channel_config_t.ledc_pre_depth : ledc channel duty depth when different channel ,select same time ,their
+ * fre_hz and ledc_pre_depth must be same
+ * @return None
+ *
+ */
+void ledc_pwm_channel_config(enum ledc_pwm_mode mode,ledc_channel_config_t* ledc_channel_config);
+
+/**
+ * @brief ledc start
+ *
+ * After call ledc_pwm_set_fre,ledc_pwm_set_duty,ledc_pwm_set_gradient need to call this function
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] channel : current configuration channel
+ *
+ * @return None
+ *
+ */
+void ledc_pwm_start(enum ledc_pwm_mode mode,enum ledc_pwm_channel channel);
+
+/**
+ * @brief ledc stop
+ *
+ * Disable ledc output,and set idle level
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] channel : current configuration channel
+ *
+ * @return None
+ *
+ */
+void ledc_pwm_stop(enum ledc_pwm_mode mode,enum ledc_pwm_channel channel,uint8_t idle_level);
+
+/**
+ * @brief ledc set fre
+ *
+ * Set ledc fre ,the unit is Hz,After the function calls the ledc_pwm_start function, the function can take effect.
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] channel : current configuration channel
+ *
+ * @param[in] fre_hz : set the ledc fre
+ *
+ * @return None
+ *
+ */
+void ledc_pwm_set_fre(enum ledc_pwm_mode mode,enum ledc_pwm_channel channel,uint32_t fre_hz);
+
+/**
+ * @brief ledc set duty
+ *
+ * Set ledc duty ,After the function calls the ledc_pwm_start function, the function can take effect.
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] channel : current configuration channel
+ *
+ * @param[in] duty : set the ledc duty ,if the ledc_pre_depth = 10,the duty range is [0,2**10]
+ *
+ * @return None
+ *
+ */
+void ledc_pwm_set_duty(enum ledc_pwm_mode mode,enum ledc_pwm_channel channel,uint16_t duty);
+
+/**
+ * @brief ledc get duty
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] channel : current configuration channel
+ *
+ *
+ * @return current ledc duty
+ *
+ */
+uint32_t ledc_pwm_get_duty(enum ledc_pwm_mode mode,enum ledc_pwm_channel channel);
+
+/**
+ * @brief ledc get fre
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] channel : current configuration channel
+ *
+ * @return current ledc fre
+ *
+ */
+uint32_t ledc_pwm_get_fre_hz(enum ledc_pwm_mode mode,enum ledc_pwm_channel channel);
+
+/**
+ * @brief register ledc interrupt occur callback function
+ *
+ * User this Function,register interrupt event callback . when ledc interrupt is triggered , the event callback
+ * will give appliacation .ledc_event_callback is called by ledc interrupt , so the ledc_event_callback
+ * should be completed in a very short period of time. If you want to deal with a lot of things,Please Creat
+ * a task ,and post message from the gpio_event_callback to the task.
+ *
+ * @param[in] func : the func will be called,when ledc interrupt is triggered ,and the param of func is the
+ * ledc interrupt channl and the mode
+ *
+ *
+ * @return None
+ *
+ */
+void ledc_register_event_callback(ledc_event_callback func);
+
+/**
+ * @brief ledc set gradient
+ *
+ * Set ledc gradient , After the function calls the ledc_pwm_start function , the function can take effect.
+ *
+ * @param[in] mode : select the ledc mode,high mode and low mode,now we only support high mode ,next will add low mode
+ *
+ * @param[in] channel : current configuration channel
+ *
+ * @param[in] duty : set the start of the gradient duty , if the ledc_pre_depth = 10,the duty range is [0,2**10]
+ *
+ * @param[in] gradule_direction : set the direction of the gradient
+ *
+ * @param[in] gradule_num : set the number of the gradient
+ *
+ * @param[in] duty_cyle_num : set how many ledc pwm tick each time the gradient lasts
+ *
+ * @param[in] duty_scale : set gradient change amplitude
+
+ * @return None
+ *
+ */
+void ledc_pwm_set_gradient(enum ledc_pwm_mode mode,uint8_t channel,uint32_t duty,enum ledc_pwm_increase_direction gradule_direction,
+ uint16_t gradule_num,uint16_t duty_cyle_num,uint16_t duty_scale);
+/**
+ * @brief register ledc interrupt handler
+ *
+ * @param uint8_t ledc_intr_num : ledc interrupt num,check the info in soc.h, and please see the core-isa.h for more details
+ * @param void (* fn)(void* ) : intr handler function
+ * @param void * arg : parameter for handler
+ *
+ * @return null
+ */
+void ledc_intr_handler_register(uint8_t ledc_intr_num,void (* fn)(void* ),void * arg);
+
+/**
+ * @brief default ledc interrupt init function to initialize the ledc intrrupt parameters.
+ *
+ * @param uint8_t pcnt_intr_num : ledc interrupt num,check the info in soc.h, and please see the core-isa.h for more details
+ *
+ * @return null
+ */
+void ledc_intr_init_default(uint8_t ledc_intr_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_LEDC_PWM_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_LEDC_PWM_STRUCT_H_
+#define _DRIVER_LEDC_PWM_STRUCT_H_
+
+#include "soc/ledc_reg.h"
+
+#define ledc_reg_s ((ledc_reg*)(DR_REG_LEDC_BASE))
+
+typedef struct ledc_pwm_s {
+ struct ledcH_channel_config{
+ union {
+ struct {
+ unsigned int timer_sel_hsch0: 2;
+ unsigned int sig_out_en_hsch0: 1;
+ unsigned int idle_lv_hsch0: 1;
+ unsigned int reserved4: 27;
+ unsigned int clk_en: 1;
+ } ;
+ uint32_t val;
+ } LEDC_HSCHX_CONF0;
+ union {
+ struct {
+ unsigned int hpoint_hsch0: 20;
+ unsigned int reserved20: 12;
+ } ;
+ uint32_t val;
+ } LEDC_HSCHX_HPOINT;
+ union {
+ struct {
+ unsigned int duty_hsch0: 25;
+ unsigned int reserved25: 7;
+ } ;
+ uint32_t val;
+ } LEDC_HSCHX_DUTY;
+ union {
+ struct {
+ unsigned int duty_scale_hsch0: 10;
+ unsigned int duty_cycle_hsch0: 10;
+ unsigned int duty_num_hsch0: 10;
+ unsigned int duty_inc_hsch0: 1;
+ unsigned int duty_start_hsch0: 1;
+ } ;
+ uint32_t val;
+ } LEDC_HSCHX_CONF1;
+ union {
+ struct {
+ unsigned int duty_hsch0: 25;
+ unsigned int reserved25: 7;
+ } ;
+ uint32_t val;
+ } LEDC_HSCHX_DUTY_R;
+ }ledch_channel_config[8];
+ struct ledcL_channel_config{
+ union {
+ struct {
+ unsigned int timer_sel_lsch0: 2;
+ unsigned int sig_out_en_lsch0: 1;
+ unsigned int idle_lv_lsch0: 1;
+ unsigned int para_up_lsch0: 1;
+ unsigned int reserved5: 27;
+ } ;
+ uint32_t val;
+ } LEDC_LSCHX_CONF0;
+ union {
+ struct {
+ unsigned int hpoint_lsch0: 20;
+ unsigned int reserved20: 12;
+ } ;
+ uint32_t val;
+ } LEDC_LSCHX_HPOINT;
+ union {
+ struct {
+ unsigned int duty_lsch0: 25;
+ unsigned int reserved25: 7;
+ } ;
+ uint32_t val;
+ } LEDC_LSCHX_DUTY;
+ union {
+ struct {
+ unsigned int duty_scale_lsch0: 10;
+ unsigned int duty_cycle_lsch0: 10;
+ unsigned int duty_num_lsch0: 10;
+ unsigned int duty_inc_lsch0: 1;
+ unsigned int duty_start_lsch0: 1;
+ } ;
+ uint32_t val;
+ } LEDC_LSCHX_CONF1;
+ union {
+ struct {
+ unsigned int duty_lsch0: 25;
+ unsigned int reserved25: 7;
+ } ;
+ uint32_t val;
+ } LEDC_LSCHX_DUTY_R;
+ }ledcl_channel_config[8];
+ struct ledcH_time_config{
+ union {
+ struct {
+ unsigned int hstimer0_lim: 5;
+ unsigned int div_num_hstimer0: 18;
+ unsigned int hstimer0_pause: 1;
+ unsigned int hstimer0_rst: 1;
+ unsigned int tick_sel_hstimer0: 1;
+ unsigned int reserved26: 6;
+ } ;
+ uint32_t val;
+ } LEDC_HSTIMERX_CONF;
+ union {
+ struct {
+ unsigned int hstimer0_cnt: 20;
+ unsigned int reserved20: 12;
+ } ;
+ uint32_t val;
+ } LEDC_HSTIMERX_VALUE;
+ }ledch_time_config[4];
+ struct ledcL_timer_config{
+ union {
+ struct {
+ unsigned int lstimer0_lim: 5;
+ unsigned int div_num_lstimer0: 18;
+ unsigned int lstimer0_pause: 1;
+ unsigned int lstimer0_rst: 1;
+ unsigned int tick_sel_lstimer0: 1;
+ unsigned int lstimer0_para_up: 1;
+ unsigned int reserved27: 5;
+ } ;
+ uint32_t val;
+ } LEDC_LSTIMERX_CONF;
+ union {
+ struct {
+ unsigned int lstimer0_cnt: 20;
+ unsigned int reserved20: 12;
+ } ;
+ uint32_t val;
+ } LEDC_LSTIMERX_VALUE;
+
+ }ledcl_time_config[4];
+ union {
+ struct {
+ unsigned int hstimer0_ovf_int_raw: 1;
+ unsigned int hstimer1_ovf_int_raw: 1;
+ unsigned int hstimer2_ovf_int_raw: 1;
+ unsigned int hstimer3_ovf_int_raw: 1;
+ unsigned int lstimer0_ovf_int_raw: 1;
+ unsigned int lstimer1_ovf_int_raw: 1;
+ unsigned int lstimer2_ovf_int_raw: 1;
+ unsigned int lstimer3_ovf_int_raw: 1;
+ unsigned int duty_chng_end_hsch0_int_raw: 1;
+ unsigned int duty_chng_end_hsch1_int_raw: 1;
+ unsigned int duty_chng_end_hsch2_int_raw: 1;
+ unsigned int duty_chng_end_hsch3_int_raw: 1;
+ unsigned int duty_chng_end_hsch4_int_raw: 1;
+ unsigned int duty_chng_end_hsch5_int_raw: 1;
+ unsigned int duty_chng_end_hsch6_int_raw: 1;
+ unsigned int duty_chng_end_hsch7_int_raw: 1;
+ unsigned int duty_chng_end_lsch0_int_raw: 1;
+ unsigned int duty_chng_end_lsch1_int_raw: 1;
+ unsigned int duty_chng_end_lsch2_int_raw: 1;
+ unsigned int duty_chng_end_lsch3_int_raw: 1;
+ unsigned int duty_chng_end_lsch4_int_raw: 1;
+ unsigned int duty_chng_end_lsch5_int_raw: 1;
+ unsigned int duty_chng_end_lsch6_int_raw: 1;
+ unsigned int duty_chng_end_lsch7_int_raw: 1;
+ unsigned int reserved24: 8;
+ } ;
+ uint32_t val;
+ } LEDC_INT_RAW;
+ union {
+ struct {
+ unsigned int hstimer0_ovf_int_st: 1;
+ unsigned int hstimer1_ovf_int_st: 1;
+ unsigned int hstimer2_ovf_int_st: 1;
+ unsigned int hstimer3_ovf_int_st: 1;
+ unsigned int lstimer0_ovf_int_st: 1;
+ unsigned int lstimer1_ovf_int_st: 1;
+ unsigned int lstimer2_ovf_int_st: 1;
+ unsigned int lstimer3_ovf_int_st: 1;
+ unsigned int duty_chng_end_hsch0_int_st: 1;
+ unsigned int duty_chng_end_hsch1_int_st: 1;
+ unsigned int duty_chng_end_hsch2_int_st: 1;
+ unsigned int duty_chng_end_hsch3_int_st: 1;
+ unsigned int duty_chng_end_hsch4_int_st: 1;
+ unsigned int duty_chng_end_hsch5_int_st: 1;
+ unsigned int duty_chng_end_hsch6_int_st: 1;
+ unsigned int duty_chng_end_hsch7_int_st: 1;
+ unsigned int duty_chng_end_lsch0_int_st: 1;
+ unsigned int duty_chng_end_lsch1_int_st: 1;
+ unsigned int duty_chng_end_lsch2_int_st: 1;
+ unsigned int duty_chng_end_lsch3_int_st: 1;
+ unsigned int duty_chng_end_lsch4_int_st: 1;
+ unsigned int duty_chng_end_lsch5_int_st: 1;
+ unsigned int duty_chng_end_lsch6_int_st: 1;
+ unsigned int duty_chng_end_lsch7_int_st: 1;
+ unsigned int reserved24: 8;
+ } ;
+ uint32_t val;
+ } LEDC_INT_ST;
+ union {
+ struct {
+ unsigned int hstimer0_ovf_int_ena: 1;
+ unsigned int hstimer1_ovf_int_ena: 1;
+ unsigned int hstimer2_ovf_int_ena: 1;
+ unsigned int hstimer3_ovf_int_ena: 1;
+ unsigned int lstimer0_ovf_int_ena: 1;
+ unsigned int lstimer1_ovf_int_ena: 1;
+ unsigned int lstimer2_ovf_int_ena: 1;
+ unsigned int lstimer3_ovf_int_ena: 1;
+ unsigned int duty_chng_end_hsch0_int_ena: 1;
+ unsigned int duty_chng_end_hsch1_int_ena: 1;
+ unsigned int duty_chng_end_hsch2_int_ena: 1;
+ unsigned int duty_chng_end_hsch3_int_ena: 1;
+ unsigned int duty_chng_end_hsch4_int_ena: 1;
+ unsigned int duty_chng_end_hsch5_int_ena: 1;
+ unsigned int duty_chng_end_hsch6_int_ena: 1;
+ unsigned int duty_chng_end_hsch7_int_ena: 1;
+ unsigned int duty_chng_end_lsch0_int_ena: 1;
+ unsigned int duty_chng_end_lsch1_int_ena: 1;
+ unsigned int duty_chng_end_lsch2_int_ena: 1;
+ unsigned int duty_chng_end_lsch3_int_ena: 1;
+ unsigned int duty_chng_end_lsch4_int_ena: 1;
+ unsigned int duty_chng_end_lsch5_int_ena: 1;
+ unsigned int duty_chng_end_lsch6_int_ena: 1;
+ unsigned int duty_chng_end_lsch7_int_ena: 1;
+ unsigned int reserved24: 8;
+ } ;
+ uint32_t val;
+ } LEDC_INT_ENA;
+ union {
+ struct {
+ unsigned int hstimer0_ovf_int_clr: 1;
+ unsigned int hstimer1_ovf_int_clr: 1;
+ unsigned int hstimer2_ovf_int_clr: 1;
+ unsigned int hstimer3_ovf_int_clr: 1;
+ unsigned int lstimer0_ovf_int_clr: 1;
+ unsigned int lstimer1_ovf_int_clr: 1;
+ unsigned int lstimer2_ovf_int_clr: 1;
+ unsigned int lstimer3_ovf_int_clr: 1;
+ unsigned int duty_chng_end_hsch0_int_clr: 1;
+ unsigned int duty_chng_end_hsch1_int_clr: 1;
+ unsigned int duty_chng_end_hsch2_int_clr: 1;
+ unsigned int duty_chng_end_hsch3_int_clr: 1;
+ unsigned int duty_chng_end_hsch4_int_clr: 1;
+ unsigned int duty_chng_end_hsch5_int_clr: 1;
+ unsigned int duty_chng_end_hsch6_int_clr: 1;
+ unsigned int duty_chng_end_hsch7_int_clr: 1;
+ unsigned int duty_chng_end_lsch0_int_clr: 1;
+ unsigned int duty_chng_end_lsch1_int_clr: 1;
+ unsigned int duty_chng_end_lsch2_int_clr: 1;
+ unsigned int duty_chng_end_lsch3_int_clr: 1;
+ unsigned int duty_chng_end_lsch4_int_clr: 1;
+ unsigned int duty_chng_end_lsch5_int_clr: 1;
+ unsigned int duty_chng_end_lsch6_int_clr: 1;
+ unsigned int duty_chng_end_lsch7_int_clr: 1;
+ unsigned int reserved24: 8;
+ } ;
+ uint32_t val;
+ } LEDC_INT_CLR;
+ union {
+ struct {
+ unsigned int apb_clk_sel: 1;
+ unsigned int reserved1: 31;
+ } ;
+ uint32_t val;
+ } LEDC_CONF;
+ uint32_t reserved_194;
+ uint32_t reserved_198;
+ uint32_t reserved_19c;
+ uint32_t reserved_1a0;
+ uint32_t reserved_1a4;
+ uint32_t reserved_1a8;
+ uint32_t reserved_1ac;
+ uint32_t reserved_1b0;
+ uint32_t reserved_1b4;
+ uint32_t reserved_1b8;
+ uint32_t reserved_1bc;
+ uint32_t reserved_1c0;
+ uint32_t reserved_1c4;
+ uint32_t reserved_1c8;
+ uint32_t reserved_1cc;
+ uint32_t reserved_1d0;
+ uint32_t reserved_1d4;
+ uint32_t reserved_1d8;
+ uint32_t reserved_1dc;
+ uint32_t reserved_1e0;
+ uint32_t reserved_1e4;
+ uint32_t reserved_1e8;
+ uint32_t reserved_1ec;
+ uint32_t reserved_1f0;
+ uint32_t reserved_1f4;
+ uint32_t reserved_1f8;
+ struct {
+ uint32_t val;
+ } LEDC_DATE1;
+}ledc_reg;
+
+#endif /* _DRIVER_LEDC_PWM_STRUCT_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_PCNT_H_
+#define _DRIVER_PCNT_H_
+
+#include <stdbool.h>
+#include "soc/dport_reg.h"
+#include "soc/pcnt_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+//register address redefine,just only use simple
+#define PCNT_UX_CONF0(Channel) (PCNT_U0_CONF0_REG+(Channel)*12)
+#define PCNT_UX_CONF1(Channel) (PCNT_U0_CONF1_REG+(Channel)*12)
+#define PCNT_UX_CONF2(Channel) (PCNT_U0_CONF2_REG+(Channel)*12)
+#define PCNT_CNT_CURRENT_VALUE(Channel) ( PCNT_U0_CNT_REG+((Channel)*4))
+#define PCNT_UX_STATUS(Channel) (PCNT_U0_STATUS_REG+(Channel)*4)
+//if user not use pin param ,please give this define
+#define PCNT_INVALID_PIN_PARAM (40)
+
+typedef enum {
+ PCNT_CHANNEL0=0,
+ PCNT_CHANNEL1=1,
+ PCNT_CHANNEL2=2,
+ PCNT_CHANNEL3=3,
+ PCNT_CHANNEL4=4,
+ PCNT_CHANNEL5=5,
+ PCNT_CHANNEL6=6,
+ PCNT_CHANNEL7=7,
+}enum_pcnt_channel_t;
+//Control Mode
+enum pcnt_ctrl_high_level{
+ PCNT_H_LEVEL_INCREASE=0,
+ PCNT_H_LEVEL_DECREASE=1,
+ PCNT_H_LEVEL_FORBIDDEN=2,
+};
+enum pcnt_ctrl_low_level{
+ PCNT_L_LEVEL_INCREASE=0,
+ PCNT_L_LEVEL_DECREASE=1,
+ PCNT_L_LEVEL_FORBIDDEN=2,
+};
+//Sig Mode
+enum pcnt_sig_positive_edge{
+ PCNT_POSEDGE_INCREASE=1,
+ PCNT_POSEDGE_DECREASE=2,
+ PCNT_POSEDGE_FORBIDDEN=0,
+};
+enum pcnt_sig_negative_edge{
+ PCNT_NEGEDGE_INCREASE=1,
+ PCNT_NEGEDGE_DECREASE=2,
+ PCNT_NEGEDGE_FORBIDDEN=0,
+};
+
+//Gate Config
+typedef struct {
+ uint8_t ctrl_pin_num;
+ uint8_t sig_pin_num;
+ enum pcnt_ctrl_high_level ctrl_high_level;
+ enum pcnt_ctrl_low_level ctrl_low_level;
+ enum pcnt_sig_positive_edge sig_positive_edge;
+ enum pcnt_sig_negative_edge sig_negative_edge;
+}pcnt_gate_t;
+//Channel Config
+typedef struct {
+ enum_pcnt_channel_t channel;
+ int16_t L_limit;
+ int16_t H_limit;
+ uint16_t Filter_tick;
+ pcnt_gate_t * Gate0;
+ pcnt_gate_t * Gate1;
+}Pcnt_channel_config;
+
+typedef enum pcnt_intr_type{
+ PCNT_CNT_EQU_THRESH1=BIT(2),
+ PCNT_CNT_EQU_THRESH0=BIT(3),
+ PCNT_CNT_LESS_THAN_LIMIT_L=BIT(4),
+ PCNT_CNT_EXCEED_LIMIT_H=BIT(5),
+ PCNT_CNT_ZERO_RELATED=BIT(6),
+}enum_intr_type_t;
+
+enum pcnt_count_zero_intr_type{
+ PCNT_CNT_INCREASE_TO_ZERO=0,
+ PCNT_CNT_DECREASE_TO_ZERO=1,
+ PCNT_CNT_NEGATIVE=2,
+ PCNT_CNT_POSITIVE=3,
+};
+
+enum pcnt_intr_mask{
+ PCNT_THRESH1_INTR_ENABLE=PCNT_THR_THRES1_EN_U0,
+ PCNT_THRESH0_INTR_ENABLE=PCNT_THR_THRES0_EN_U0,
+ PCNT_L_LIMIT_INTR_ENABLE=PCNT_THR_L_LIM_EN_U0,
+ PCNT_H_LIMIT_INTR_ENABLE=PCNT_THR_H_LIM_EN_U0,
+ PCNT_ZERO_INTR_ENABLE=PCNT_THR_ZERO_EN_U0,
+ PCNT_ALL_INTR_ENABLE = (PCNT_THR_THRES1_EN_U0|PCNT_THR_THRES0_EN_U0|PCNT_THR_L_LIM_EN_U0|PCNT_THR_H_LIM_EN_U0|PCNT_THR_ZERO_EN_U0)
+};
+
+typedef struct{
+ enum_pcnt_channel_t channel;
+ int16_t thres1;
+ int16_t thres0;
+ uint32_t PcntIntrEnMask;
+}pcnt_intr_config;
+
+typedef struct pcnt_event_message{
+ enum_pcnt_channel_t channel;
+ enum_intr_type_t intr_type;
+}pcnt_event_mes;
+
+typedef void (*pcnt_event_callback)(pcnt_event_mes pcnt_message);
+
+/**
+ * @brief resert pcnt counter,the pcnt cnt is cleared zero
+ *
+ * @param[in] channel : the channel of the pcnt
+ *
+ * @return true : reset succed
+ * fail : reset fail
+ *
+ */
+bool pcnt_reset_counter(enum_pcnt_channel_t channel);
+
+/**
+ * @brief start pnct counter
+ *
+ * @param[in] channel : the channel of the pcnt
+ *
+ * @return None
+ *
+ */
+void pcnt_start_counter(enum_pcnt_channel_t channel);
+
+/**
+ * @brief get the pcnt counter value
+ *
+ * @param[in] channel : the channel of the pcnt
+ *
+ * @return the value of the pcnt
+ *
+ */
+int16_t pcnt_get_counter_value(enum_pcnt_channel_t channel);
+
+/**
+ * @brief enable the pcnt pcnt interrupt
+ *
+ * @param[in] channel : the channel of the pcnt
+ *
+ * @return None
+ *
+ */
+void pcnt_enable_channel_intr(enum_pcnt_channel_t channel);
+
+/**
+ * @brief disable the pcnt pcnt interrupt
+ *
+ * @param[in] channel : the channel of the pcnt
+ *
+ * @return None
+ *
+ */
+void pcnt_disable_channel_intr(enum_pcnt_channel_t channel);
+/**
+ * @brief register pcnt interrupt occur callback function
+ *
+ * Use this Function,register interrupt event callback . when pcnt interrupt is triggered , the event callback
+ * will give appliacation .pcnt_event_callback is called by pcnt interrupt , so the gpio_event_callback
+ * should be completed in a very short period of time. If you want to deal with a lot of things,Please Creat
+ * a task ,and post message from the pcnt_event_callback to the task.
+ *
+ * @param[in] func : the func will be called,when pcnt interrupt is triggered ,and the param of func is the
+ * number of the pnct channel occurs interrupt and intr type
+ *
+ *
+ * @return None
+ *
+ */
+void pcnt_register_event_callback(pcnt_event_callback func);
+
+/**
+ * @brief config the pcnt pcnt interrupt
+ *
+ * @param[in] intr_config intr_config.channel : the channel of pcnt
+ * intr_config.thres1 : the intr threshold1
+ * intr_config.thres0 : the intr threshold0
+ * intr_config.PcntIntrEnMask : reference the enum pcnt_intr_mask.if user want to enable thres1 intr
+ * and thres0 intr,PcntIntrEnMask=PCNT_THRESH1_INTR_ENABLE|PCNT_THRESH0_INTR_ENABLE.
+ *
+ * @return None
+ *
+ */
+void pcnt_set_intr(pcnt_intr_config* intr_config);
+
+/**
+ * @brief pcnt common configuration
+ *
+ * @param[in] channel_config channel_config.channel : the channel of pcnt
+ * channel_config.L_limit : the counter range [L_limit,H_limit]
+ * channel_config.H_limit : the counter range [L_limit,H_limit]
+ * channel_config.Filter_tick : the counter filte tick cnt ,tick=80M
+ * channel_config.Gate0 : config the Gate0
+ * channel_config.Gate1 : config the Gate1
+ *
+ * @return None
+ *
+ */
+void pcnt_init_channel(Pcnt_channel_config *channel_config);
+
+/**
+ * @brief register pcnt interrupt handler
+ *
+ * @param uint8_t pcnt_intr_num : pcnt interrupt num,check the info in soc.h, and please see the core-isa.h for more details
+ * @param void (* fn)(void* ) : intr handler function
+ * @param void * arg : parameter for handler
+ *
+ * @return null
+ */
+void pcnt_intr_handler_register(uint8_t pcnt_intr_num,void (* fn)(void* ),void * arg);
+
+/**
+ * @brief default pcnt interrupt init function to initialize the pcnt intrrupt parameters.
+ *
+ * @param uint8_t pcnt_intr_num : pcnt interrupt num,check the info in soc.h, and please see the core-isa.h for more details
+ *
+ * @return null
+ */
+void pcnt_intr_init_default(uint8_t pcnt_intr_num);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_PCNT_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_RMT_CTRL_H_
+#define _DRIVER_RMT_CTRL_H_
+
+#include <stdbool.h>
+#include "soc/rmt_reg.h"
+#include "soc/dport_reg.h"
+#include "driver/gpio.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RMT_CHANNEL_MEMORY_CHAR_CNT (256)
+#define RMT_CHANNEL_MEMORY_WORD_CNT (RMT_CHANNEL_MEMORY_CHAR_CNT/4)
+#define RMT_DIV_CLK_KHZ (320)//Do not change this
+
+#define RMT_CHXCONF1(CHANNEL) ((RMT_CH0CONF1_REG)+((CHANNEL)*0X08))
+#define RMT_CHXCONF0(CHANNEL) ((RMT_CH0CONF0_REG)+((CHANNEL)*0X08))
+#define RMT_CHXSTATUS(CHANNEL) ((RMT_CH0STATUS_REG)+((CHANNEL)*0X04))
+#define RMT_CHXCARRIER_DUTY(CHANNEL) ((RMT_CH0CARRIER_DUTY_REG)+(CHANNEL)*0X04)
+#define RMT_CHXADDR_REG(CHANNEL) (RMT_CH0ADDR_REG+((CHANNEL)*0X04))
+#define RMT_CHXSTATUS_REG(CHANNEL) (RMT_CH0STATUS_REG+((CHANNEL)*0X04))
+#define RMT_CHX_MEMEOY(channel) (DR_REG_RMT_BASE+0X800+0X4*(channel*0x40))
+
+//Config0
+#define RMT_GET_REG_CARRIER_OUT_LV_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_OUT_LV_CH0_V, RMT_CARRIER_OUT_LV_CH0_S)
+#define RMT_SET_REG_CARRIER_OUT_LV_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_OUT_LV_CH0_V,(val),RMT_CARRIER_OUT_LV_CH0_S)
+#define RMT_GET_REG_CARRIER_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_EN_CH0_V, RMT_CARRIER_EN_CH0_S)
+#define RMT_SET_REG_CARRIER_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_CARRIER_EN_CH0_V,(val),RMT_CARRIER_EN_CH0_S)
+#define RMT_GET_REG_MEM_SIZE_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_MEM_SIZE_CH0_V, RMT_MEM_SIZE_CH0_S)
+#define RMT_SET_REG_MEM_SIZE_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_MEM_SIZE_CH0_V,(val),RMT_MEM_SIZE_CH0_S)
+#define RMT_GET_REG_IDLE_THRES_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_IDLE_THRES_CH0_V, RMT_IDLE_THRES_CH0_S)
+#define RMT_SET_REG_IDLE_THRES_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_IDLE_THRES_CH0_V,(val),RMT_IDLE_THRES_CH0_S)
+#define RMT_GET_REG_DIV_CNT_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF0(CHANNEL),RMT_DIV_CNT_CH0_V, RMT_DIV_CNT_CH0_S)
+#define RMT_SET_REG_DIV_CNT_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF0(CHANNEL),RMT_DIV_CNT_CH0_V,(val),RMT_DIV_CNT_CH0_S)
+//Config1
+#define RMT_GET_REG_IDLE_OUT_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_IDLE_OUT_EN_CH0_V, RMT_IDLE_OUT_EN_CH0_S)
+#define RMT_SET_REG_IDLE_OUT_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_IDLE_OUT_EN_CH0_V,(val),RMT_IDLE_OUT_EN_CH0_S)
+#define RMT_GET_REG_IDLE_OUT_LV_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_IDLE_OUT_LV_CH0_V, RMT_IDLE_OUT_LV_CH0_S)
+#define RMT_SET_REG_IDLE_OUT_LV_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_IDLE_OUT_LV_CH0_V,(val),RMT_IDLE_OUT_LV_CH0_S)
+#define RMT_GET_REG_REF_ALWAYS_ON_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_REF_ALWAYS_ON_CH0_V, RMT_REF_ALWAYS_ON_CH0_S)
+#define RMT_SET_REG_REF_ALWAYS_ON_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_REF_ALWAYS_ON_CH0_V,(val),RMT_REF_ALWAYS_ON_CH0_S)
+#define RMT_GET_REG_REF_CNT_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_REF_CNT_RST_CH0_V, RMT_REF_CNT_RST_CH0_S)
+#define RMT_SET_REG_REF_CNT_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_REF_CNT_RST_CH0_V,(val),RMT_REF_CNT_RST_CH0_S)
+#define RMT_GET_REG_RX_FILTER_THRES_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_RX_FILTER_THRES_CH0_V, RMT_RX_FILTER_THRES_CH0_S)
+#define RMT_SET_REG_RX_FILTER_THRES_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_RX_FILTER_THRES_CH0_V,(val),RMT_RX_FILTER_THRES_CH0_S)
+#define RMT_GET_REG_RX_FILTER_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_RX_FILTER_EN_CH0_V, RMT_RX_FILTER_EN_CH0_S)
+#define RMT_SET_REG_RX_FILTER_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_RX_FILTER_EN_CH0_V,(val),RMT_RX_FILTER_EN_CH0_S)
+#define RMT_GET_REG_TX_CONTI_MODE_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_TX_CONTI_MODE_CH0_V, RMT_TX_CONTI_MODE_CH0_S)
+#define RMT_SET_REG_TX_CONTI_MODE_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_TX_CONTI_MODE_CH0_V,(val),RMT_TX_CONTI_MODE_CH0_S)
+#define RMT_GET_REG_MEM_OWNER_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_MEM_OWNER_CH0_V, RMT_MEM_OWNER_CH0_S)
+#define RMT_SET_REG_MEM_OWNER_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL),RMT_MEM_OWNER_CH0_V,(val),RMT_MEM_OWNER_CH0_S)
+#define RMT_GET_REG_APB_MEM_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL), RMT_APB_MEM_RST_CH0_V, RMT_APB_MEM_RST_CH0_S)
+#define RMT_SET_REG_APB_MEM_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_APB_MEM_RST_CH0_V,(val),RMT_APB_MEM_RST_CH0_S)
+#define RMT_GET_REG_MEM_RD_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_MEM_RD_RST_CH0_V, RMT_MEM_RD_RST_CH0_S)
+#define RMT_SET_REG_MEM_RD_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_MEM_RD_RST_CH0_V,(val),RMT_MEM_RD_RST_CH0_S)
+#define RMT_GET_REG_MEM_WR_RST_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_MEM_WR_RST_CH0_V, RMT_MEM_WR_RST_CH0_S)
+#define RMT_SET_REG_MEM_WR_RST_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_MEM_WR_RST_CH0_V,(val),RMT_MEM_WR_RST_CH0_S)
+#define RMT_GET_REG_RX_EN_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_RX_EN_CH0_V, RMT_RX_EN_CH0_S)
+#define RMT_SET_REG_RX_EN_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_RX_EN_CH0_V,(val),RMT_RX_EN_CH0_S)
+#define RMT_GET_REG_TX_START_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCONF1(CHANNEL) , RMT_TX_START_CH0_V, RMT_TX_START_CH0_S)
+#define RMT_SET_REG_TX_START_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCONF1(CHANNEL) ,RMT_TX_START_CH0_V,(val),RMT_TX_START_CH0_S)
+//Carrier
+#define RMT_GET_REG_CARRIER_HIGH_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCARRIER_DUTY(CHANNEL) , RMT_CARRIER_HIGH_CH0_V, RMT_CARRIER_HIGH_CH0_S)
+#define RMT_SET_REG_CARRIER_HIGH_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCARRIER_DUTY(CHANNEL) ,RMT_CARRIER_HIGH_CH0_V,(val),RMT_CARRIER_HIGH_CH0_S)
+#define RMT_GET_REG_CARRIER_LOW_CHX(CHANNEL) GET_PERI_REG_BITS2(RMT_CHXCARRIER_DUTY(CHANNEL) , RMT_CARRIER_LOW_CH0_V, RMT_CARRIER_LOW_CH0_S)
+#define RMT_SET_REG_CARRIER_LOW_CHX(CHANNEL,val) SET_PERI_REG_BITS(RMT_CHXCARRIER_DUTY(CHANNEL) ,RMT_CARRIER_LOW_CH0_V,(val),RMT_CARRIER_LOW_CH0_S)
+
+#define RMT_GET_MEM_TX_WRAP_EN() GET_PERI_REG_BITS2(RMT_APB_CONF_REG , RMT_MEM_TX_WRAP_EN_V, RMT_MEM_TX_WRAP_EN_S)
+#define RMT_SET_MEM_TX_WRAP_EN(val) SET_PERI_REG_BITS(RMT_APB_CONF_REG ,RMT_MEM_TX_WRAP_EN_V,(val),RMT_MEM_TX_WRAP_EN_S)
+#define RMT_GET_APB_FIFO_MASK() GET_PERI_REG_BITS2(RMT_APB_CONF_REG , RMT_APB_FIFO_MASK_V, RMT_APB_FIFO_MASK_S)
+#define RMT_SET_APB_FIFO_MASK(val) SET_PERI_REG_BITS(RMT_APB_CONF_REG ,RMT_APB_FIFO_MASK_V,(val),RMT_APB_FIFO_MASK_S)
+
+enum rmt_channel{
+ RMT_CTRL_CHANNEL0=0, /**< Rmt Channel0 */
+ RMT_CTRL_CHANNEL1, /**< Rmt Channel1 */
+ RMT_CTRL_CHANNEL2, /**< Rmt Channel2 */
+ RMT_CTRL_CHANNEL3, /**< Rmt Channel3 */
+ RMT_CTRL_CHANNEL4, /**< Rmt Channel4 */
+ RMT_CTRL_CHANNEL5, /**< Rmt Channel5 */
+ RMT_CTRL_CHANNEL6, /**< Rmt Channel6 */
+ RMT_CTRL_CHANNEL7, /**< Rmt Channel7 */
+};
+enum rmt_ram_owner{
+ RMT_RAM_OWNER_HARDWARE=0,/**< Rmt Rx mode ,Memory owner RMT_RAM_OWNER_HARDWARE */
+ RMT_RAM_OWNER_SOFTWARE=1,/**< Rmt Rx mode ,Memory owner RMT_RAM_OWNER_SOFTWARE */
+};
+enum rmt_source_clk{
+ RMT_BASECLK_REF=0,/**< Rmt Clk is Refclk defautl is 1MHz */
+ RMT_BASECLK_APB,/**< Rmt Clk is APB CLK defautl is 80MHz */
+};
+enum rmt_ctrl_mode{
+ RMT_TX_MODE=0,/**< Rmt TX Mode */
+ RMT_RX_MODE, /**< Rmt RX Mode */
+};
+enum rmt_idle_level{
+ RMT_IDLE_LOW_LEVEL=0,/**< Rmt TX IDLE Low Level */
+ RMT_IDLE_HIGH_LEVEL, /**< Rmt TX IDLE High Level */
+};
+enum rmt_carrier_level{
+ RMT_CARRIER_LOW_LEVEL=0,/**< Rmt Carrier Low Level */
+ RMT_CARRIER_HIGH_LEVEL, /**< Rmt Carrier High Level */
+};
+
+typedef struct rmt_ctrl_tx{
+ uint32_t carrier_fre_Hz; /**< Rmt Carrier Fre */
+ uint8_t carrier_duty; /**< Rmt Carrier duty */
+ enum rmt_idle_level idle_level; /**< Rmt Idle level */
+ enum rmt_carrier_level carrier_level;/**< Rmt Carrier level */
+}rmt_ctrl_tx_config_t;
+
+typedef struct rmt_ctrl_rx{
+ uint8_t filter_tick_cnt; /**< Rmt filter tick cnt */
+ uint16_t rx_threshold_tick_cnt;/**< Rmt rx interrupt threshold */
+}rmt_ctrl_rx_config_t;
+
+typedef struct rmt_ctrl_config{
+ enum rmt_ctrl_mode rmt_mode;
+ enum rmt_channel channel;
+ gpio_num_t gpio_num;
+ uint8_t channel_mem_cnt;//NAME
+ bool intr_enable;
+ union{
+ rmt_ctrl_tx_config_t tx_config;
+ rmt_ctrl_rx_config_t rx_config;
+ }mode_config;
+}rmt_ctrl_channel_config_t;
+
+typedef struct rmt_event_message{
+ enum rmt_ctrl_mode mode;
+ enum rmt_channel channel;
+}rmt_event_msg_t;
+
+typedef void (*rmt_event_callback)(rmt_event_msg_t rmt_message);
+
+/**
+ * @brief register rmt interrupt occur callback function
+ *
+ * Use this Function,register interrupt event callback . when rmt interrupt is triggered , the event callback
+ * will give appliacation .rmt_event_callback is called by rmt interrupt , so the rmt_event_callback
+ * should be completed in a very short period of time. If you want to deal with a lot of things,Please Creat
+ * a task ,and post message from the rmt_event_callback to the task.
+
+ * @param[in] func : the func will be called,when rmt interrupt is triggered ,and the param of func is the
+ * mode of rmt and channel of rmt
+ *
+ *
+ * @return None
+ *
+ */
+void rmt_register_event_callback(rmt_event_callback func);
+
+/**
+ * @brief rmt common configuration
+ *
+ * User this Function,config rmt the channel tx mode or rx mode
+ *
+ * @param[in] rmt_config rmt_config.rmt_mode : select rmt tx mode or rx mode.
+ * rmt_config.rmt_channel : current configuration channel.
+ * rmt_config.gpio_num : tx or rx mode ,signagle use the gpio.
+ * rmt_config.channel_mem_cnt : the tx or rx used the memory block cnt,every mem cnt have 256Byte contents
+ * rmt_config.intr_enable : enable or disable tx or rx interrupt.when enable tx mode , send the tx memory end ,will trigger
+ * tx event . when enable rx mode ,rx line idle time beyond rx_threshold_tick_cnt will trigger rx
+ * event.
+ * rmt_config.mode_config.tx_config : tx common config.
+ * rmt_config.mode_config.rx_config : rx common config.
+ *
+ * @return None
+ *
+ */
+void rmt_ctrl_init(rmt_ctrl_channel_config_t* rmt_config);
+
+/**
+ * @brief write rmt tx memory
+ *
+ * When rmt tx memory content is 0x00,the tx will stop,and trigger tx intr event
+ *
+ * @param[in] channel : rmt tx channel
+ * mem : write the mem to tx memory
+ * cnt : the cnt max is rmt_config.channel_mem_cnt *32
+ *
+ * @return None
+ *
+ */
+void rmt_ctrl_tx_wr_memory(enum rmt_channel channel,uint32_t* mem,uint16_t cnt);
+
+/**
+ * @brief rmt rx start
+ *
+ * @param[in] channel : rmt rx channel
+ *
+ * @return None
+ *
+ */
+void rmt_ctrl_rx_start(enum rmt_channel channel);
+
+/**
+ * @brief rmt tx start
+ *
+ * @param[in] channel : rmt tx channel
+ *
+ * @return None
+ *
+ */
+void rmt_ctrl_tx_start(enum rmt_channel channel);
+
+/**
+ * @brief rmt read rx memory
+ *
+ * @param[in] channel : rmt rx channel
+ *
+ * @param[in] mem : the rx memory data copy to the mem,the mem content cnt = rmt_config.channel_mem_cnt *32
+ *
+ * @return rx memory number of received data
+ *
+ */
+uint16_t rmt_ctrl_rx_rd_memory(enum rmt_channel channel,uint32_t* mem);
+/**
+ * @brief register rmt interrupt handler
+ *
+ * @param uint8_t ledc_intr_num : rmt interrupt num,check the info in soc.h, and please see the core-isa.h for more details
+ * @param void (* fn)(void* ) : intr handler function
+ * @param void * arg : parameter for handler
+ *
+ * @return null
+ */
+void rmt_intr_handler_register(uint8_t rmt_intr_num,void (* fn)(void* ),void * arg);
+/**
+ * @brief default rmt interrupt init function to initialize the rmt intrrupt parameters.
+ *
+ * @param uint8_t rmt_intr_num : ledc interrupt num,check the info in soc.h, and please see the core-isa.h for more details
+ *
+ * @return null
+ */
+
+void rmt_intr_init_default(uint8_t rmt_intr_num);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_RMT_CTRL_H_ */
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_SPI_H_
+#define _DRIVER_SPI_H_
+#include "soc/dport_reg.h"
+#include "spi.h"
+#include "soc/spi_reg.h"
+#include <esp_types.h>
+#include "dma.h"
+#include "esp_err.h"
+
+#define ETS_SPI_INUM 8
+#define ETS_HSIP_INUM 8
+#define ETS_I2S_INUM 9
+#define ETS_RTC_INUM 9
+#define ETS_RMT_CTRL_INUM 9
+#define ETS_GPIO_INUM 18
+#define ETS_MAX_INUM 16
+#define ETS_I2C0_INUM 17
+//#define ETS_I2S0_INUM 17
+#define ETS_SPI1_INUM 17
+#define ETS_SPI2_INUM 17
+#define ETS_SPI3_INUM 17
+#define ETS_PCNT_INUM 17
+#define ETS_LEDC_INUM 18
+
+
+//*****************************************************************************
+//
+// Make sure all of the definitions in this header have a C binding.
+//
+//*****************************************************************************
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @brief Support SPI1/SPI2/SPI3 module.
+ *
+ */
+typedef enum {
+ SPI_NUM_SPI1 = 0x1,
+ SPI_NUM_SPI2 = 0x2,
+ SPI_NUM_SPI3 = 0x3,
+ SPI_NUM_MAX = SPI_NUM_SPI3,
+} spi_num_t;
+
+/**
+ * @brief The SPI module can work in either master or slave mode.
+ *
+ */
+typedef enum {
+ SPI_MODE_MASTER = 0,
+ SPI_MODE_SLAVE = 1,
+} spi_mode_t;
+
+/**
+ * @brief SPI sub mode
+ *
+ * Support 4 sub modes based on SPI clock polarity and phase.
+ * SPI_CPOL SPI_CPHA SubMode
+ * 0 0 0
+ * 0 1 1
+ * 1 0 2
+ * 1 1 3
+ */
+typedef enum {
+ SPI_SUBMODE_0 = 0,
+ SPI_SUBMODE_1 = 1,
+ SPI_SUBMODE_2 = 2,
+ SPI_SUBMODE_3 = 3,
+} spi_sub_mode_t;
+
+/**
+ * @brief The SPI module working speed.
+ *
+ * @attention Max speed 80MHz
+ *
+ */
+typedef enum {
+ SPI_SPEED_2MHZ = 40,
+ SPI_SPEED_5MHZ = 16,
+ SPI_SPEED_8MHZ = 10,
+ SPI_SPEED_10MHZ = 8,
+ SPI_SPEED_16MHZ = 5,
+ SPI_SPEED_20MHZ = 4,
+} spi_speed_t;
+
+/**
+ * @brief The SPI mode working speed.
+ *
+ */
+typedef enum {
+ SPI_BIT_ORDER_MSB_FIRST = 0,
+ SPI_BIT_ORDER_LSB_FIRST = 1,
+} spi_bit_order_t;
+
+// @brief SPI interrupt source defined.
+typedef enum {
+ SPI_INT_SRC_TRANS_DONE = SPI_TRANS_DONE,
+ SPI_INT_SRC_WR_STA_DONE = SPI_SLV_WR_STA_DONE,
+ SPI_INT_SRC_RD_STA_DONE = SPI_SLV_RD_STA_DONE,
+ SPI_INT_SRC_WR_BUF_DONE = SPI_SLV_WR_BUF_DONE,
+ SPI_INT_SRC_RD_BUF_DONE = SPI_SLV_RD_BUF_DONE,
+ SPI_INT_SRC_ONE_BUF_RECV_DONE = SPI_IN_SUC_EOF_INT_ENA,
+ SPI_INT_SRC_ONE_BUF_SEND_DONE = SPI_OUT_EOF_INT_ENA,
+} spi_int_src_t;
+
+/**
+ * @brief The SPI mode working speed.
+ *
+ */
+typedef enum {
+ SPI_WORK_MODE_HALF = 0,
+ SPI_WORK_MODE_FULL = 1,
+} spi_work_mode_t;
+
+/**
+ * @brief The SPI DMA channels.
+ *
+ */
+typedef enum {
+ SPI_DMA_CHANNEL_0 = 1,
+ SPI_DMA_CHANNEL_1 = 2,
+} spi_dma_channel_t;
+
+/**
+ * @brief The SPI dma direction.
+ *
+ */
+typedef enum {
+ SPI_DMA_DIR_IN = 1,
+ SPI_DMA_DIR_OUT = 2,
+} spi_dma_dir_t;
+
+#pragma pack(1)
+/**
+ * @brief SPI attribute
+ */
+typedef struct {
+ spi_mode_t mode; ///< Master or slave mode
+ spi_sub_mode_t sub_mode; ///< SPI SPI_CPOL SPI_CPHA mode
+ spi_speed_t speed; ///< SPI Clock
+ spi_bit_order_t bit_order; ///< SPI bit order
+ spi_work_mode_t half_mode; ///< Half or Full work mode
+} spi_attr_t;
+
+/**
+* @brief SPI attribute
+*/
+typedef struct {
+ uint16_t cmd; ///< Command value
+ uint8_t cmd_len; ///< Command byte length
+ uint32_t *addr; ///< Point to address value
+ uint8_t addr_len; ///< Address byte length
+ uint32_t *tx_data; ///< Point to send data buffer
+ uint8_t tx_data_len; ///< Send data byte length.
+ uint32_t *rx_data; ///< Point to recevie data buffer
+ uint8_t rx_data_len; ///< Recevie Data byte length.
+} spi_data_t;
+
+// SPI DMA attribite
+typedef struct {
+ spi_num_t spi_num; ///< Spi number
+ uint32_t mode; ///< Spi work mode
+ uint32_t buf_size; ///< Size of buffer
+ spi_dma_dir_t dir; ///< Direction of data,in or out.
+ spi_dma_channel_t channel; ///< Channel of DMA
+ ping_pong_buf_t *buf; ///< Buffer address
+} spi_dma_attr_t;
+#pragma pack()
+
+/**
+ * @brief Get SPI ping buffer address.
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return uint32_t*, NULL:indicates parameter error, others indicates ping buffer address.
+ */
+uint32_t* spi_dma_ping_buf_get(spi_dma_attr_t *obj);
+
+/**
+ * @brief Get SPI pong buffer address.
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return uint32_t*, NULL:indicates parameter error, others indicates pong buffer address.
+ */
+uint32_t* spi_dma_pong_buf_get(spi_dma_attr_t *obj);
+
+/**
+ * @brief Get without working ping-pong buffer address.
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return uint32_t*, NULL:indicates parameter error, others indicates not working buffer address.
+ */
+uint32_t* spi_dma_status_get(spi_dma_attr_t *obj);
+
+/**
+ * @brief Configrate the Ping-Pong buffer to the destination
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return None.
+ */
+int32_t spi_dma_memcpy(spi_dma_attr_t *obj, void *src, uint32_t len);
+
+/**
+ * @brief Configrate the Ping-Pong buffer to the destination
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return None.
+ */
+void spi_dma_dest_add_set(spi_dma_attr_t *obj);
+
+/**
+ * @brief Reset the SPI DMA instance
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ * @param [in] isr
+ * Indicates which function to be called, when interrupt hanpened.
+ *
+ * @return None.
+ */
+void spi_dma_rest(spi_dma_attr_t *obj);
+
+/**
+ * @brief Initialize DMA and create a SPI DMA instance
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ * @param [in] isr
+ * Indicates which function to be called, when interrupt hanpened.
+ *
+ * @return -1:indicates parameter error, -2: DMA buffer init failure, others indicates success.
+ */
+int spi_dma_init(spi_dma_attr_t *obj, void *isr);
+
+/**
+ * @brief Destroy the SPI DMA instance
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return int, -1:indicates parameter error, others indicates success.
+ */
+int spi_dma_uninit(spi_dma_attr_t *obj);
+
+/**
+ * @brief Configrate the Ping-Pong buffer to the destination
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return None.
+ */
+void spi_dma_int_enable(spi_num_t spiNum, spi_int_src_t intSrc);
+
+/**
+ * @brief Configrate the Ping-Pong buffer to the destination
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return None.
+ */
+void spi_dma_int_disable(spi_num_t spiNum, spi_int_src_t intSrc);
+
+/**
+ * @brief Configrate the Ping-Pong buffer to the destination
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return None.
+ */
+void spi_dma_int_clear(spi_num_t spiNum);
+
+/**
+ * @brief Configrate the Ping-Pong buffer to the destination
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return None.
+ */
+int32_t spi_dma_int_status_get(spi_num_t spiNum);
+
+/**
+ * @brief Start e SPI DMA instance
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ * @param [in] len
+ * Indicates how many data to be called.
+ *
+ * @return None.
+ */
+void spi_dma_start(spi_dma_attr_t *obj, uint32_t len);
+
+/**
+ * @brief Stop the SPI DMA transmit
+ *
+ * @param [in] obj
+ * Pointer to a struct spi_dma_attr_t that indicates SPI DMA working attribution.
+ *
+ * @return None.
+ */
+void spi_dma_stop(spi_dma_attr_t *obj);
+
+/**
+ * @brief Initialize SPI module.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ * @param [in] pAttr
+ * Pointer to a struct spi_attr_t that indicates SPI working attribution.
+ *
+ * @return void.
+ */
+void spi_init(spi_num_t spiNum, spi_attr_t* pAttr);
+
+/**
+ * @brief Set slave address value by master.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ * @param [in] addr
+ * Slave address to be set.
+ *
+ * @return void.
+ */
+void spi_master_cfg_addr(spi_num_t spiNum, uint32_t addr);
+
+/**
+ * @brief Set command value by master.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ * @param [in] cmd
+ * Command will be send to slave.
+ *
+ * @return void.
+ */
+void spi_master_cfg_cmd(spi_num_t spiNum, uint32_t cmd);
+
+/**
+ * @brief Send data to slave from master.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ * @param [in] pInData
+ * Pointer to a spi_data_t strcuture that indicates data, address and command will be send.
+ *
+ * @return int, -1:indicates failure,others indicates success.
+ */
+int spi_master_send_data(spi_num_t spiNum, spi_data_t* pInData);
+
+/**
+ * @brief Receive data from slave by master.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ * @param [in] pOutData
+ * Point to data buffer.
+ *
+ * @return int, -1:indicates failure,others indicates success.
+ *
+ */
+int spi_master_recv_data(spi_num_t spiNum, spi_data_t* pData);
+
+/**
+ * @brief Load data to slave send buffer.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ * @param [in] pOutData
+ * Point to data buffer.
+ * @param [in] outLen
+ * The number of bytes to be set.
+ *
+ * @return int, -1:indicates failure,others indicates success.
+ */
+int spi_slave_send_data(spi_num_t spiNum, uint32_t *pOutData, uint8_t outLen);
+
+/**
+ * @brief Receive data by slave.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ * @param [in] isrFunc
+ * isrFunc is a pointer to the function to be called when the SPI interrupt occurs.
+ *
+ * @return int, -1:indicates failure,others indicates success.
+ */
+int spi_slave_recv_data(spi_num_t spiNum, void(*isrFunc)(void*));
+
+/**
+ * @brief Set slave status by master.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ *
+ * @param [in] data
+ * Data will be write to slave SPI_WR_STATUS.
+ *
+ * @return void.
+ */
+void spi_master_send_status(spi_num_t spiNum, uint8_t data);
+
+/**
+ * @brief Get salve status by master.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ *
+ * @return int, -1: indicates failure; other value in slave status.
+ */
+int spi_master_recv_status(spi_num_t spiNum);
+
+/**
+ * @brief Enable SPI module interrupt source.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ *
+ * @param [in] intSrc
+ * Indicates which interrupt source to enable.
+ *
+ * @return void.
+ */
+void spi_int_enable(spi_num_t spiNum, spi_int_src_t intSrc);
+
+/**
+ * @brief Disable SPI module interrupt source.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ *
+ * @param [in] intSrc
+ * Indicates which interrupt source to disable.
+ *
+ * @return void.
+ */
+void spi_int_disable(spi_num_t spiNum, spi_int_src_t intSrc);
+
+/**
+ * @brief Clear all of spi interrupt.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ *
+ * @return void.
+ */
+void spi_int_clear(spi_num_t spiNum);
+
+/**
+ * @brief Get the spi interrupt status.
+ *
+ * @param [in] spiNum
+ * Indicates which submode to be used.
+ *
+ * @return void.
+ */
+int32_t spi_int_status_get(spi_num_t spiNum);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SPI_H__
--- /dev/null
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+\r
+#ifndef _DRIVER_TOUCH_PAD_H_\r
+#define _DRIVER_TOUCH_PAD_H_\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+#define ETS_RTC_INTR_INUM 19 \r
+\r
+\r
+typedef enum{\r
+ TOUCH_PAD_NUM0=0, //GPIO4\r
+ TOUCH_PAD_NUM1, //GPIO0\r
+ TOUCH_PAD_NUM2, //GPIO2\r
+ TOUCH_PAD_NUM3, //GPIO15\r
+ TOUCH_PAD_NUM4, //GPIO13\r
+ TOUCH_PAD_NUM5, //GPIO12\r
+ TOUCH_PAD_NUM6, //GPIO14\r
+ TOUCH_PAD_NUM7, //GPIO27\r
+ TOUCH_PAD_NUM8, //GPIO33\r
+ TOUCH_PAD_NUM9, //GPIO32\r
+ TOUCH_PAD_MAX,\r
+}enum_touch_pad_t;\r
+\r
+typedef struct touch_message{\r
+ enum_touch_pad_t touch_num;\r
+}touch_message_t;\r
+typedef void (*touch_event_callback)(touch_message_t touch_mes);\r
+/**\r
+* @brief touch module int\r
+*\r
+*This function int touch pad module ,enable touch module\r
+*\r
+* @return None \r
+* \r
+*/\r
+void touch_module_init();\r
+\r
+/**\r
+* @brief config touch pad intr callback thresold\r
+*\r
+*When you touch the pad ,touch_pad_register reduce .When the touch_pad_register less than threshold\r
+*will trigger the touch event callback\r
+*\r
+* @param[in] touch_num : config touch num\r
+*\r
+* @param[in] threshold : interrupt threshold ,When the touch_pad_register less than threshold£¬\r
+* will trigger the touch event callback.User can use touch_pad_read function\r
+* to determine the threshold.\r
+*\r
+* @return None \r
+* \r
+*/\r
+void touch_pad_config(enum_touch_pad_t touch_num,uint16_t threshold);\r
+\r
+/**\r
+* @brief register touch pad interrupt occur callback function\r
+*\r
+* Use this Function,register interrupt event callback . when touch pad interrupt is triggered , the event callback\r
+* will give appliacation .touch_event_callback is called by touch interrupt , so the touch_event_callback\r
+* should be completed in a very short period of time. If you want to deal with a lot of things,Please Creat\r
+* a task ,and post message from the gpio_event_callback to the task.\r
+*\r
+* @param[in] func : the func will be called,when touch interrupt is triggered ,and the param of func is the \r
+* number of the touch pad num occurs interrupt\r
+*\r
+*\r
+* @return None \r
+* \r
+*/\r
+void touch_module_register_event_callback(touch_event_callback touch_event_cb);\r
+\r
+/**\r
+* @brief get touch pad touch_pad_register number\r
+*\r
+*User can use this function to determine the the interrupt threshold .When you do not touch the \r
+*pad ,read the touch_pad_read number(NumNotTouch) by the touch_pad_register.When you touch the pad ,read the touch_pad_register\r
+*number(NumTouch) by the touch_pad_read.Normal NumNotTouch>NumTouch,so you can select a interrupt threshold\r
+*\r
+* @param[in] touch_num : touch num\r
+*\r
+*\r
+* @return -1 : the touch num is err\r
+* Other : the number of the touch_pad_read\r
+* \r
+*/\r
+int32_t touch_pad_read(enum_touch_pad_t touch_num);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP32 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_TIMER_H__
+#define __ESP_TIMER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "esp_types.h"
+/* timer related */
+typedef void os_timer_func_t(void *timer_arg);
+
+typedef struct _os_timer_t {
+ struct _os_timer_t *timer_next;
+ void *timer_handle;
+ uint32_t timer_expire;
+ uint32_t timer_period;
+ os_timer_func_t *timer_func;
+ bool timer_repeat_flag;
+ void *timer_arg;
+} os_timer_t;
+
+/** \defgroup Timer_APIs Software timer APIs
+ * @brief Software timer APIs
+ *
+ * Timers of the following interfaces are software timers. Functions of the timers are executed during the tasks.
+ * Since a task can be stopped, or be delayed because there are other tasks with higher priorities, the following os_timer interfaces cannot guarantee the precise execution of the timers.
+ * - For the same timer, os_timer_arm (or os_timer_arm_us) cannot be invoked repeatedly. os_timer_disarm should be invoked first.
+ * - os_timer_setfn can only be invoked when the timer is not enabled, i.e., after os_timer_disarm or before os_timer_arm (or os_timer_arm_us).
+ *
+ */
+
+/** @addtogroup Timer_APIs
+ * @{
+ */
+
+/**
+ * @brief Set the timer callback function.
+ *
+ * @attention 1. The callback function must be set in order to enable the timer.
+ * @attention 2. Operating system scheduling is disabled in timer callback.
+ *
+ * @param os_timer_t *ptimer : Timer structure
+ * @param os_timer_func_t *pfunction : timer callback function
+ * @param void *parg : callback function parameter
+ *
+ * @return null
+ */
+void os_timer_setfn(os_timer_t *ptimer, os_timer_func_t *pfunction, void *parg);
+
+/**
+ * @brief Enable the millisecond timer.
+ *
+ * @param os_timer_t *ptimer : timer structure
+ * @param uint32_t milliseconds : Timing, unit: millisecond, the maximum value allowed is 0x41893
+ * @param bool repeat_flag : Whether the timer will be invoked repeatedly or not
+ *
+ * @return null
+ */
+void os_timer_arm(os_timer_t *ptimer, uint32_t msec, bool repeat_flag);
+
+/**
+ * @brief Disarm the timer
+ *
+ * @param os_timer_t *ptimer : Timer structure
+ *
+ * @return null
+ */
+void os_timer_disarm(os_timer_t *ptimer);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
projects / esp-idf / commitdiff