]> granicus.if.org Git - llvm/commitdiff
[Mem2Reg] Simplify rewriteSingleStoreAlloca
authorFangrui Song <maskray@google.com>
Sun, 14 Apr 2019 05:48:13 +0000 (05:48 +0000)
committerFangrui Song <maskray@google.com>
Sun, 14 Apr 2019 05:48:13 +0000 (05:48 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358349 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Transforms/Utils/PromoteMemoryToRegister.cpp

index 74019c5d302ad683c2c35d363326a23cf66dbe66..28462e8c8b65ab34e16d5dcf91b866d6ae00e232 100644 (file)
@@ -362,10 +362,8 @@ static bool rewriteSingleStoreAlloca(AllocaInst *AI, AllocaInfo &Info,
 
   for (auto UI = AI->user_begin(), E = AI->user_end(); UI != E;) {
     Instruction *UserInst = cast<Instruction>(*UI++);
-    if (!isa<LoadInst>(UserInst)) {
-      assert(UserInst == OnlyStore && "Should only have load/stores");
+    if (UserInst == OnlyStore)
       continue;
-    }
     LoadInst *LI = cast<LoadInst>(UserInst);
 
     // Okay, if we have a load from the alloca, we want to replace it with the
@@ -385,8 +383,7 @@ static bool rewriteSingleStoreAlloca(AllocaInst *AI, AllocaInfo &Info,
           Info.UsingBlocks.push_back(StoreBB);
           continue;
         }
-      } else if (LI->getParent() != StoreBB &&
-                 !DT.dominates(StoreBB, LI->getParent())) {
+      } else if (!DT.dominates(StoreBB, LI->getParent())) {
         // If the load and store are in different blocks, use BB dominance to
         // check their relationships.  If the store doesn't dom the use, bail
         // out.