[x86] adjust LEA tests for better coverage; NFC

The scale can 1, 2, or 3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358539 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/lea-dagdag.ll b/test/CodeGen/X86/lea-dagdag.ll
index 4fe8fa350c9cca8a7a109e7c585f8bdf6e7a0d46..f1e9d60e6481ccc7b93e42352dc8236fc8f02c5a 100644 (file)
--- a/test/CodeGen/X86/lea-dagdag.ll
+++ b/test/CodeGen/X86/lea-dagdag.ll
@@ -40,11 +40,11 @@ define i32 @and_i8_zext_shl_add_i32(i32 %t0, i8 %t1) {
 ; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
 ; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
 ; CHECK-NEXT:    andl $8, %esi
-; CHECK-NEXT:    leal (%rdi,%rsi,4), %eax
+; CHECK-NEXT:    leal (%rdi,%rsi,8), %eax
 ; CHECK-NEXT:    retq
   %t4 = and i8 %t1, 8
   %t5 = zext i8 %t4 to i32
-  %sh = shl i32 %t5, 2
+  %sh = shl i32 %t5, 3
   %t6 = add i32 %sh, %t0
   ret i32 %t6
 }
@@ -53,12 +53,12 @@ define i32 @and_i8_shl_zext_add_i32(i32 %t0, i8 %t1) {
 ; CHECK-LABEL: and_i8_shl_zext_add_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $8, %sil
-; CHECK-NEXT:    shlb $2, %sil
+; CHECK-NEXT:    shlb $3, %sil
 ; CHECK-NEXT:    movzbl %sil, %eax
 ; CHECK-NEXT:    addl %edi, %eax
 ; CHECK-NEXT:    retq
   %t4 = and i8 %t1, 8
-  %sh = shl i8 %t4, 2
+  %sh = shl i8 %t4, 3
   %t5 = zext i8 %sh to i32
   %t6 = add i32 %t5, %t0
   ret i32 %t6
@@ -99,11 +99,11 @@ define i64 @and_i8_zext_shl_add_i64(i64 %t0, i8 %t1) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
 ; CHECK-NEXT:    andl $8, %esi
-; CHECK-NEXT:    leaq (%rdi,%rsi,4), %rax
+; CHECK-NEXT:    leaq (%rdi,%rsi,2), %rax
 ; CHECK-NEXT:    retq
   %t4 = and i8 %t1, 8
   %t5 = zext i8 %t4 to i64
-  %sh = shl i64 %t5, 2
+  %sh = shl i64 %t5, 1
   %t6 = add i64 %sh, %t0
   ret i64 %t6
 }
@@ -112,12 +112,12 @@ define i64 @and_i8_shl_zext_add_i64(i64 %t0, i8 %t1) {
 ; CHECK-LABEL: and_i8_shl_zext_add_i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andb $8, %sil
-; CHECK-NEXT:    shlb $2, %sil
+; CHECK-NEXT:    addb %sil, %sil
 ; CHECK-NEXT:    movzbl %sil, %eax
 ; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    retq
   %t4 = and i8 %t1, 8
-  %sh = shl i8 %t4, 2
+  %sh = shl i8 %t4, 1
   %t5 = zext i8 %sh to i64
   %t6 = add i64 %t5, %t0
   ret i64 %t6
@@ -128,11 +128,11 @@ define i64 @and_i32_zext_shl_add_i64(i64 %t0, i32 %t1) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
 ; CHECK-NEXT:    andl $8, %esi
-; CHECK-NEXT:    leaq (%rdi,%rsi,4), %rax
+; CHECK-NEXT:    leaq (%rdi,%rsi,8), %rax
 ; CHECK-NEXT:    retq
   %t4 = and i32 %t1, 8
   %t5 = zext i32 %t4 to i64
-  %sh = shl i64 %t5, 2
+  %sh = shl i64 %t5, 3
   %t6 = add i64 %sh, %t0
   ret i64 %t6
 }
@@ -142,13 +142,42 @@ define i64 @and_i32_shl_zext_add_i64(i64 %t0, i32 %t1) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
 ; CHECK-NEXT:    andl $8, %esi
-; CHECK-NEXT:    leal (,%rsi,4), %eax
+; CHECK-NEXT:    leal (,%rsi,8), %eax
 ; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    retq
   %t4 = and i32 %t1, 8
-  %sh = shl i32 %t4, 2
+  %sh = shl i32 %t4, 3
   %t5 = zext i32 %sh to i64
   %t6 = add i64 %t5, %t0
   ret i64 %t6
 }
 
+define i64 @and_i32_zext_shl_add_i64_overshift(i64 %t0, i32 %t1) {
+; CHECK-LABEL: and_i32_zext_shl_add_i64_overshift:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT:    andl $8, %esi
+; CHECK-NEXT:    shlq $4, %rsi
+; CHECK-NEXT:    leaq (%rsi,%rdi), %rax
+; CHECK-NEXT:    retq
+  %t4 = and i32 %t1, 8
+  %t5 = zext i32 %t4 to i64
+  %sh = shl i64 %t5, 4
+  %t6 = add i64 %sh, %t0
+  ret i64 %t6
+}
+
+define i64 @and_i32_shl_zext_add_i64_overshift(i64 %t0, i32 %t1) {
+; CHECK-LABEL: and_i32_shl_zext_add_i64_overshift:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT:    andl $8, %esi
+; CHECK-NEXT:    shll $4, %esi
+; CHECK-NEXT:    leaq (%rsi,%rdi), %rax
+; CHECK-NEXT:    retq
+  %t4 = and i32 %t1, 8
+  %sh = shl i32 %t4, 4
+  %t5 = zext i32 %sh to i64
+  %t6 = add i64 %t5, %t0
+  ret i64 %t6
+}