[AArch64] Adjust the cost model for Exynos M1 and M2

Refine the model of loads and stores using the register offset addressing
modes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313554 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index 89fa5a0f363074ac0facd83b0239574579bf6fd5..163891a9d012903c251deda7cc50a0fc43508557 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -736,6 +736,7 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
 
 bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
   unsigned Imm, Shift;
+  AArch64_AM::ShiftExtendType Ext;
 
   switch (MI.getOpcode()) {
   default:
@@ -779,8 +780,8 @@ bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
   case AArch64::SUBXrs:
     Imm = MI.getOperand(3).getImm();
     Shift = AArch64_AM::getShiftValue(Imm);
-    return (Shift == 0 ||
-            (Shift <= 3 && AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL));
+    Ext = AArch64_AM::getShiftType(Imm);
+    return (Shift == 0 || (Shift <= 3 && Ext == AArch64_AM::LSL));
 
   // WriteIEReg
   case AArch64::ADDSWrx:
@@ -797,9 +798,62 @@ bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
   case AArch64::SUBXrx64:
     Imm = MI.getOperand(3).getImm();
     Shift = AArch64_AM::getArithShiftValue(Imm);
-    return (Shift == 0 ||
-            (Shift <= 3 &&
-             AArch64_AM::getArithExtendType(Imm) == AArch64_AM::UXTX));
+    Ext = AArch64_AM::getArithExtendType(Imm);
+    return (Shift == 0 || (Shift <= 3 && Ext == AArch64_AM::UXTX));
+
+  case AArch64::PRFMroW:
+  case AArch64::PRFMroX:
+
+  // WriteLDIdx
+  case AArch64::LDRBBroW:
+  case AArch64::LDRBBroX:
+  case AArch64::LDRHHroW:
+  case AArch64::LDRHHroX:
+  case AArch64::LDRSBWroW:
+  case AArch64::LDRSBWroX:
+  case AArch64::LDRSBXroW:
+  case AArch64::LDRSBXroX:
+  case AArch64::LDRSHWroW:
+  case AArch64::LDRSHWroX:
+  case AArch64::LDRSHXroW:
+  case AArch64::LDRSHXroX:
+  case AArch64::LDRSWroW:
+  case AArch64::LDRSWroX:
+  case AArch64::LDRWroW:
+  case AArch64::LDRWroX:
+  case AArch64::LDRXroW:
+  case AArch64::LDRXroX:
+
+  case AArch64::LDRBroW:
+  case AArch64::LDRBroX:
+  case AArch64::LDRDroW:
+  case AArch64::LDRDroX:
+  case AArch64::LDRHroW:
+  case AArch64::LDRHroX:
+  case AArch64::LDRSroW:
+  case AArch64::LDRSroX:
+
+  // WriteSTIdx
+  case AArch64::STRBBroW:
+  case AArch64::STRBBroX:
+  case AArch64::STRHHroW:
+  case AArch64::STRHHroX:
+  case AArch64::STRWroW:
+  case AArch64::STRWroX:
+  case AArch64::STRXroW:
+  case AArch64::STRXroX:
+
+  case AArch64::STRBroW:
+  case AArch64::STRBroX:
+  case AArch64::STRDroW:
+  case AArch64::STRDroX:
+  case AArch64::STRHroW:
+  case AArch64::STRHroX:
+  case AArch64::STRSroW:
+  case AArch64::STRSroX:
+    Imm = MI.getOperand(3).getImm();
+    Ext = AArch64_AM::getMemExtendType(Imm);
+    return (Ext == AArch64_AM::SXTX || Ext == AArch64_AM::UXTX);
   }
 }
 

diff --git a/lib/Target/AArch64/AArch64SchedM1.td b/lib/Target/AArch64/AArch64SchedM1.td
index 5327f8f5c53eac306bfd876246ba6672476e2b34..041894dcc27b6f1af910664ba50f81554f826405 100644 (file)
--- a/lib/Target/AArch64/AArch64SchedM1.td
+++ b/lib/Target/AArch64/AArch64SchedM1.td
@@ -88,16 +88,19 @@ def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkFastPred, [M1WriteA1,
                                                                    M1WriteC1]>]>;
 
 def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
-def M1WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteL5,
-                                                            M1WriteA1]>,
-                                   SchedVar<NoSchedPred,   [M1WriteL5]>]>;
+def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
+                                   SchedVar<NoSchedPred,         [M1WriteA1,
+                                                                  M1WriteL5]>]>;
 
 def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
 def M1WriteS2 : SchedWriteRes<[M1UnitS]> { let Latency = 2; }
 def M1WriteS4 : SchedWriteRes<[M1UnitS]> { let Latency = 4; }
-def M1WriteSX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteS2,
-                                                            M1WriteA1]>,
-                                   SchedVar<NoSchedPred,   [M1WriteS1]>]>;
+def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
+                                   SchedVar<NoSchedPred,         [M1WriteA1,
+                                                                  M1WriteS1]>]>;
+def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
+                                   SchedVar<NoSchedPred,         [M1WriteA1,
+                                                                  M1WriteS2]>]>;
 
 def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
                                       SchedVar<NoSchedPred,   [ReadDefault]>]>;
@@ -369,6 +372,8 @@ def : InstRW<[WriteLD,
               WriteLDHi,
               WriteAdr,
               M1WriteA1], (instregex "^LDP(SW|W|X)(post|pre)")>;
+def : InstRW<[M1WriteLX,
+              ReadAdrBase], (instregex "^PRFMro[WX]")>;
 
 // Store instructions.
 
@@ -401,20 +406,30 @@ def : InstRW<[M1WriteNEONI],  (instregex "^FMOV[DS][WX](High)?r")>;
 // FP load instructions.
 def : InstRW<[WriteVLD,
               WriteAdr,
-              M1WriteA1], (instregex "^LDP[DS](post|pre)")>;
+              M1WriteA1],   (instregex "^LDP[DS](post|pre)")>;
 def : InstRW<[WriteVLD,
               WriteVLD,
               WriteAdr,
-              M1WriteA1], (instregex "^LDPQ(post|pre)")>;
+              M1WriteA1],   (instregex "^LDPQ(post|pre)")>;
+def : InstRW<[M1WriteLX,
+              ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>;
+def : InstRW<[M1WriteA1,
+              M1WriteL5,
+              ReadAdrBase], (instregex "^LDRQro[WX]")>;
 
 // FP store instructions.
 def : InstRW<[WriteVST,
               WriteAdr,
-              M1WriteA1], (instregex "^STP[DS](post|pre)")>;
+              M1WriteA1],   (instregex "^STP[DS](post|pre)")>;
 def : InstRW<[WriteVST,
               WriteVST,
               WriteAdr,
-              M1WriteA1], (instregex "^STPQ(post|pre)")>;
+              M1WriteA1],   (instregex "^STPQ(post|pre)")>;
+def : InstRW<[M1WriteSY,
+              ReadAdrBase], (instregex "^STR[BDHS]ro[WX]")>;
+def : InstRW<[M1WriteA1,
+              M1WriteS2,
+              ReadAdrBase], (instregex "^STRQro[WX]")>;
 
 // ASIMD instructions.
 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;