ordered_cpu_features = [
"FPU", "Cyrix", "AMD", "MMX", "3DNow", "SMM", "SSE", "SSE2",
"SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
- "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "CVT16"]
+ "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4"]
unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
# Predefined VEX prefix field values
add_insn("movntss", "movntss")
-#####################################################################
-# AMD CVT16 instructions
-#####################################################################
-
-add_group("vcvtph2ps",
- cpu=["CVT16"],
- xop=128,
- opcode=[0x08, 0xA0],
- operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Mem", size=64, relaxed=True, dest="EA"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-add_group("vcvtph2ps",
- cpu=["CVT16"],
- xop=128,
- opcode=[0x08, 0xA0],
- operands=[Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="SIMDReg", size=128, dest="EA"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-add_group("vcvtph2ps",
- cpu=["CVT16"],
- xop=256,
- opcode=[0x08, 0xA0],
- operands=[Operand(type="SIMDReg", size=256, dest="Spare"),
- Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-add_insn("vcvtph2ps", "vcvtph2ps")
-
-add_group("vcvtps2ph",
- cpu=["CVT16"],
- xop=128,
- opcode=[0x08, 0xA1],
- operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-add_group("vcvtps2ph",
- cpu=["CVT16"],
- xop=128,
- opcode=[0x08, 0xA1],
- operands=[Operand(type="SIMDReg", size=128, dest="EA"),
- Operand(type="SIMDReg", size=128, dest="Spare"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-add_group("vcvtps2ph",
- cpu=["CVT16"],
- xop=256,
- opcode=[0x08, 0xA1],
- operands=[Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"),
- Operand(type="SIMDReg", size=256, dest="Spare"),
- Operand(type="Imm", size=8, relaxed=True, dest="Imm")])
-add_insn("vcvtps2ph", "vcvtps2ph")
-
#####################################################################
# AMD XOP instructions
#####################################################################
+++ /dev/null
-; BITS=16 to minimize output length
-[bits 16]
-vcvtph2ps xmm1, xmm4, 5 ; 8F E8 78 A0 314 05
-vcvtph2ps xmm2, [0], byte 5 ; 8F E8 78 A0 026 00 00 05
-vcvtph2ps xmm3, qword [0], 5 ; 8F E8 78 A0 036 00 00 05
-vcvtph2ps ymm1, xmm4, 5 ; 8F E8 7C A0 314 05
-vcvtph2ps ymm2, [0], byte 5 ; 8F E8 7C A0 026 00 00 05
-vcvtph2ps ymm3, dqword [0], 5 ; 8F E8 7C A0 036 00 00 05
-
-vcvtps2ph xmm1, xmm4, 5 ; 8F E8 78 A1 341 05
-vcvtps2ph [0], xmm2, byte 5 ; 8F E8 78 A1 026 00 00 05
-vcvtps2ph qword [0], xmm3, 5 ; 8F E8 78 A1 036 00 00 05
-vcvtps2ph xmm1, ymm4, 5 ; 8F E8 7C A1 341 05
-vcvtps2ph [0], ymm2, byte 5 ; 8F E8 7C A1 026 00 00 05
-vcvtps2ph dqword [0], ymm3, 5 ; 8F E8 7C A1 036 00 00 05
-
if (data >= PROC_bulldozer) {
BitVector_Bit_On(cpu, CPU_XOP);
BitVector_Bit_On(cpu, CPU_FMA4);
- BitVector_Bit_On(cpu, CPU_CVT16);
}
if (data >= PROC_k10)
BitVector_Bit_On(cpu, CPU_SSE4a);
noxop, x86_cpu_clear, CPU_XOP
fma4, x86_cpu_set, CPU_FMA4
nofma4, x86_cpu_clear, CPU_FMA4
-cvt16, x86_cpu_set, CPU_CVT16
-nocvt16, x86_cpu_clear, CPU_CVT16
# Change NOP patterns
basicnop, x86_nop, X86_NOP_BASIC
intelnop, x86_nop, X86_NOP_INTEL