]> granicus.if.org Git - yasm/commitdiff
Add support for Nehalem XSAVE instructions and CPU feature.
authorPeter Johnson <peter@tortall.net>
Fri, 22 Feb 2008 04:48:56 +0000 (04:48 -0000)
committerPeter Johnson <peter@tortall.net>
Fri, 22 Feb 2008 04:48:56 +0000 (04:48 -0000)
svn path=/trunk/yasm/; revision=2042

modules/arch/x86/gen_x86_insn.py
modules/arch/x86/tests/Makefile.inc
modules/arch/x86/tests/xsave.asm [new file with mode: 0644]
modules/arch/x86/tests/xsave.hex [new file with mode: 0644]
modules/arch/x86/x86arch.h
modules/arch/x86/x86cpu.gperf

index fd923d4fbbdc0c64f9bc0c532fd58b785e981c18..d850feed903e4728bbec497a96af9247d8efb155 100755 (executable)
@@ -5323,6 +5323,18 @@ add_insn("pshaq", "sse5psh", modifiers=[0x07])
 
 # roundps, roundpd, roundss, roundsd, ptest are in SSE4.1
 
+#####################################################################
+# Intel XSAVE instructions
+#####################################################################
+add_insn("xgetbv", "threebyte", modifiers=[0x0F, 0x01, 0xD0],
+         cpu=["XSAVE", "386"])
+add_insn("xsetbv", "threebyte", modifiers=[0x0F, 0x01, 0xD1],
+         cpu=["XSAVE", "386", "Priv"])
+add_insn("xsave", "twobytemem", modifiers=[4, 0x0F, 0xAE],
+         cpu=["XSAVE", "386"])
+add_insn("xrstor", "twobytemem", modifiers=[5, 0x0F, 0xAE],
+         cpu=["XSAVE", "386"])
+
 #####################################################################
 # AMD 3DNow! instructions
 #####################################################################
index b9f35d2b3c1c1e5c754c947578b26c5a312af1fe..b500f4193f016320b611123e55067c114b9c0195 100644 (file)
@@ -204,6 +204,8 @@ EXTRA_DIST += modules/arch/x86/tests/xchg64.asm
 EXTRA_DIST += modules/arch/x86/tests/xchg64.hex
 EXTRA_DIST += modules/arch/x86/tests/xmm64.asm
 EXTRA_DIST += modules/arch/x86/tests/xmm64.hex
+EXTRA_DIST += modules/arch/x86/tests/xsave.asm
+EXTRA_DIST += modules/arch/x86/tests/xsave.hex
 
 EXTRA_DIST += modules/arch/x86/tests/gas32/Makefile.inc
 EXTRA_DIST += modules/arch/x86/tests/gas64/Makefile.inc
diff --git a/modules/arch/x86/tests/xsave.asm b/modules/arch/x86/tests/xsave.asm
new file mode 100644 (file)
index 0000000..6105879
--- /dev/null
@@ -0,0 +1,4 @@
+xsave [0]
+xrstor [0]
+xgetbv
+xsetbv
diff --git a/modules/arch/x86/tests/xsave.hex b/modules/arch/x86/tests/xsave.hex
new file mode 100644 (file)
index 0000000..2b6d09a
--- /dev/null
@@ -0,0 +1,16 @@
+0f 
+ae 
+26 
+00 
+00 
+0f 
+ae 
+2e 
+00 
+00 
+0f 
+01 
+d0 
+0f 
+01 
+d1 
index b5c0f0910ece8befe56cf89e132b01bb5582369c..bd53e373287a483954ad356f74e5454409156b88 100644 (file)
@@ -65,6 +65,7 @@
 #define CPU_SSE42   31      /* Streaming SIMD extensions 4.2 required */
 #define CPU_SSE4a   32      /* AMD Streaming SIMD extensions 4a required */
 #define CPU_SSE5    33      /* AMD Streaming SIMD extensions 5 required */
+#define CPU_XSAVE   33      /* Intel XSAVE instruction */
 
 /* Technically not CPU capabilities, they do affect what instructions are
  * available.  These are tested against BITS==64.
index 5487d32099312243ceb98b32db67c85f73a49e76..c3f27e5b75180330198568b66877512ae0c1dfc9 100644 (file)
@@ -58,8 +58,10 @@ x86_cpu_intel(wordptr cpu, unsigned int data)
         BitVector_Bit_On(cpu, CPU_Prot);
     if (data >= PROC_386)
         BitVector_Bit_On(cpu, CPU_SMM);
-    if (data >= PROC_nehalem)
+    if (data >= PROC_nehalem) {
         BitVector_Bit_On(cpu, CPU_SSE42);
+        BitVector_Bit_On(cpu, CPU_XSAVE);
+    }
     if (data >= PROC_penryn)
         BitVector_Bit_On(cpu, CPU_SSE41);
     if (data >= PROC_conroe)
@@ -326,6 +328,8 @@ sse4,               x86_cpu_set_sse4,       0
 nosse4,                x86_cpu_clear_sse4,     0
 sse5,          x86_cpu_set,    CPU_SSE5
 nosse5,                x86_cpu_clear,  CPU_SSE5
+xsave,         x86_cpu_set,    CPU_XSAVE
+noxsave,       x86_cpu_clear,  CPU_XSAVE
 %%
 
 void