GlobalISel: mark G_BRCOND on s1 as legal.

It's going to be a TBNZ (at -O0) anyway, so the high bits don't matter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284070 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index adda760cb1ddd81701bd2bb5fee650893ba7040e..4f921e8d8efde193ce55b5a8c79add53ab797247 100644 (file)
--- a/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -156,9 +156,8 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
   }
 
   // Control-flow
-  setAction({G_BRCOND, s32}, Legal);
-  for (auto Ty : {s1, s8, s16})
-    setAction({G_BRCOND, Ty}, WidenScalar);
+  for (auto Ty : {s1, s8, s16, s32})
+    setAction({G_BRCOND, Ty}, Legal);
 
   // Select
   for (auto Ty : {s1, s8, s16, s32, s64})

diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index 29cc49ff9d957c3b354b7ee2adebfd0c06af12e3..1817a9101511e54a922ec2f56c04d85b48a7d83c 100644 (file)
--- a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -47,6 +47,7 @@ registers:
   - { id: 30, class: _ }
   - { id: 31, class: _ }
   - { id: 32, class: _ }
+  - { id: 33, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
@@ -58,8 +59,7 @@ body: |
     %1(p0) = G_INTTOPTR %0
     %2(s64) = G_PTRTOINT %1
 
-    ; CHECK: [[TST32:%[0-9]+]](s32) = G_ANYEXT %3
-    ; CHECK: G_BRCOND [[TST32]](s32), %bb.1.next
+    ; CHECK: G_BRCOND %3(s1), %bb.1.next
     %3(s1) = G_TRUNC %0
     G_BRCOND %3, %bb.1.next