[MIPS GlobalISel] Select integer to floating point conversions

Select G_SITOFP and G_UITOFP for MIPS32.

Differential Revision: https://reviews.llvm.org/D63542

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363912 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index e2b0fb753e9ba5fbeb55be9570f20fdadeab0937..d153a35ded468dbd43fc7935b008bf1ebba48705 100644 (file)
--- a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -435,12 +435,12 @@ LegalizerHelper::libcall(MachineInstr &MI) {
     // FIXME: Support other types
     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
-    if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
+    if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
       return UnableToLegalize;
     LegalizeResult Status = conversionLibcall(
         MI, MIRBuilder,
         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
-        Type::getInt32Ty(Ctx));
+        FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
     if (Status != Legalized)
       return Status;
     break;

diff --git a/lib/Target/Mips/MipsLegalizerInfo.cpp b/lib/Target/Mips/MipsLegalizerInfo.cpp
index 0f7c4dfb1488309bacdda2e7ca43fcd5152373e0..465355d66b6a13832bca2edbea59dcc6229db623 100644 (file)
--- a/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -120,6 +120,16 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
       .libcallForCartesianProduct({s64}, {s64, s32})
       .minScalar(0, s32);
 
+  // Int to FP conversion instructions
+  getActionDefinitionsBuilder(G_SITOFP)
+      .legalForCartesianProduct({s64, s32}, {s32})
+      .libcallForCartesianProduct({s64, s32}, {s64})
+      .minScalar(1, s32);
+
+  getActionDefinitionsBuilder(G_UITOFP)
+      .libcallForCartesianProduct({s64, s32}, {s64})
+      .minScalar(1, s32);
+
   computeTables();
   verify(*ST.getInstrInfo());
 }

diff --git a/lib/Target/Mips/MipsRegisterBankInfo.cpp b/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 736756ba3bff65f2c12deaaec5f05876e3ae1454..b9d7f0468fafc8ae0d0246fb69215ca673107849 100644 (file)
--- a/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -182,6 +182,17 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     });
     break;
   }
+  case G_SITOFP: {
+    unsigned SizeInt = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
+    unsigned SizeFP = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
+    assert((SizeInt == 32) && "Unsupported integer size");
+    assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
+    OperandsMapping =
+        getOperandsMapping({SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
+                                         : &Mips::ValueMappings[Mips::DPRIdx],
+                            &Mips::ValueMappings[Mips::GPRIdx]});
+    break;
+  }
   case G_CONSTANT:
   case G_FRAME_INDEX:
   case G_GLOBAL_VALUE:

diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir
new file mode 100644 (file)
index 0000000..9f0e455
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @i32tof32() {entry: ret void}
+  define void @i32tof64() {entry: ret void}
+
+...
+---
+name:            i32tof32
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i32tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP32: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
+    ; FP32: $f0 = COPY [[PseudoCVT_S_W]]
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: i32tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP64: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
+    ; FP64: $f0 = COPY [[PseudoCVT_S_W]]
+    ; FP64: RetRA implicit $f0
+    %0:gprb(s32) = COPY $a0
+    %1:fprb(s32) = G_SITOFP %0(s32)
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            i32tof64
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i32tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP32: [[PseudoCVT_D32_W:%[0-9]+]]:afgr64 = PseudoCVT_D32_W [[COPY]]
+    ; FP32: $d0 = COPY [[PseudoCVT_D32_W]]
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: i32tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; FP64: [[PseudoCVT_D64_W:%[0-9]+]]:fgr64 = PseudoCVT_D64_W [[COPY]]
+    ; FP64: $d0 = COPY [[PseudoCVT_D64_W]]
+    ; FP64: RetRA implicit $d0
+    %0:gprb(s32) = COPY $a0
+    %1:fprb(s64) = G_SITOFP %0(s32)
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir b/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
new file mode 100644 (file)
index 0000000..00abc06
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
@@ -0,0 +1,369 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @i64tof32() {entry: ret void}
+  define void @i32tof32() {entry: ret void}
+  define void @i16tof32() {entry: ret void}
+  define void @i8tof32() {entry: ret void}
+  define void @i64tof64() {entry: ret void}
+  define void @i32tof64() {entry: ret void}
+  define void @i16tof64() {entry: ret void}
+  define void @i8tof64() {entry: ret void}
+  define void @u64tof32() {entry: ret void}
+  define void @u64tof64() {entry: ret void}
+
+...
+---
+name:            i64tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; FP32-LABEL: name: i64tof32
+    ; FP32: liveins: $a0, $a1
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $a0 = COPY [[COPY]](s32)
+    ; FP32: $a1 = COPY [[COPY1]](s32)
+    ; FP32: JAL &__floatdisf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+    ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f0 = COPY [[COPY2]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: i64tof32
+    ; FP64: liveins: $a0, $a1
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $a0 = COPY [[COPY]](s32)
+    ; FP64: $a1 = COPY [[COPY1]](s32)
+    ; FP64: JAL &__floatdisf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+    ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f0 = COPY [[COPY2]](s32)
+    ; FP64: RetRA implicit $f0
+    %1:_(s32) = COPY $a0
+    %2:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
+    %3:_(s32) = G_SITOFP %0(s64)
+    $f0 = COPY %3(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            i32tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i32tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
+    ; FP32: $f0 = COPY [[SITOFP]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: i32tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
+    ; FP64: $f0 = COPY [[SITOFP]](s32)
+    ; FP64: RetRA implicit $f0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_SITOFP %0(s32)
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            i16tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i16tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
+    ; FP32: $f0 = COPY [[SITOFP]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: i16tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
+    ; FP64: $f0 = COPY [[SITOFP]](s32)
+    ; FP64: RetRA implicit $f0
+    %1:_(s32) = COPY $a0
+    %0:_(s16) = G_TRUNC %1(s32)
+    %2:_(s32) = G_SITOFP %0(s16)
+    $f0 = COPY %2(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            i8tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i8tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
+    ; FP32: $f0 = COPY [[SITOFP]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: i8tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
+    ; FP64: $f0 = COPY [[SITOFP]](s32)
+    ; FP64: RetRA implicit $f0
+    %1:_(s32) = COPY $a0
+    %0:_(s8) = G_TRUNC %1(s32)
+    %2:_(s32) = G_SITOFP %0(s8)
+    $f0 = COPY %2(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            i64tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; FP32-LABEL: name: i64tof64
+    ; FP32: liveins: $a0, $a1
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $a0 = COPY [[COPY]](s32)
+    ; FP32: $a1 = COPY [[COPY1]](s32)
+    ; FP32: JAL &__floatdidf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0
+    ; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d0 = COPY [[COPY2]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: i64tof64
+    ; FP64: liveins: $a0, $a1
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $a0 = COPY [[COPY]](s32)
+    ; FP64: $a1 = COPY [[COPY1]](s32)
+    ; FP64: JAL &__floatdidf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0_64
+    ; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d0 = COPY [[COPY2]](s64)
+    ; FP64: RetRA implicit $d0
+    %1:_(s32) = COPY $a0
+    %2:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
+    %3:_(s64) = G_SITOFP %0(s64)
+    $d0 = COPY %3(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            i32tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i32tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
+    ; FP32: $d0 = COPY [[SITOFP]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: i32tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
+    ; FP64: $d0 = COPY [[SITOFP]](s64)
+    ; FP64: RetRA implicit $d0
+    %0:_(s32) = COPY $a0
+    %1:_(s64) = G_SITOFP %0(s32)
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            i16tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i16tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
+    ; FP32: $d0 = COPY [[SITOFP]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: i16tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
+    ; FP64: $d0 = COPY [[SITOFP]](s64)
+    ; FP64: RetRA implicit $d0
+    %1:_(s32) = COPY $a0
+    %0:_(s16) = G_TRUNC %1(s32)
+    %2:_(s64) = G_SITOFP %0(s16)
+    $d0 = COPY %2(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            i8tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i8tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
+    ; FP32: $d0 = COPY [[SITOFP]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: i8tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+    ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
+    ; FP64: $d0 = COPY [[SITOFP]](s64)
+    ; FP64: RetRA implicit $d0
+    %1:_(s32) = COPY $a0
+    %0:_(s8) = G_TRUNC %1(s32)
+    %2:_(s64) = G_SITOFP %0(s8)
+    $d0 = COPY %2(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            u64tof32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; FP32-LABEL: name: u64tof32
+    ; FP32: liveins: $a0, $a1
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $a0 = COPY [[COPY]](s32)
+    ; FP32: $a1 = COPY [[COPY1]](s32)
+    ; FP32: JAL &__floatundisf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+    ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f0 = COPY [[COPY2]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: u64tof32
+    ; FP64: liveins: $a0, $a1
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $a0 = COPY [[COPY]](s32)
+    ; FP64: $a1 = COPY [[COPY1]](s32)
+    ; FP64: JAL &__floatundisf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
+    ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f0 = COPY [[COPY2]](s32)
+    ; FP64: RetRA implicit $f0
+    %1:_(s32) = COPY $a0
+    %2:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
+    %3:_(s32) = G_UITOFP %0(s64)
+    $f0 = COPY %3(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            u64tof64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; FP32-LABEL: name: u64tof64
+    ; FP32: liveins: $a0, $a1
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $a0 = COPY [[COPY]](s32)
+    ; FP32: $a1 = COPY [[COPY1]](s32)
+    ; FP32: JAL &__floatundidf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0
+    ; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d0 = COPY [[COPY2]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: u64tof64
+    ; FP64: liveins: $a0, $a1
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $a0 = COPY [[COPY]](s32)
+    ; FP64: $a1 = COPY [[COPY1]](s32)
+    ; FP64: JAL &__floatundidf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0_64
+    ; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d0 = COPY [[COPY2]](s64)
+    ; FP64: RetRA implicit $d0
+    %1:_(s32) = COPY $a0
+    %2:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
+    %3:_(s64) = G_UITOFP %0(s64)
+    $d0 = COPY %3(s64)
+    RetRA implicit $d0
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
new file mode 100644 (file)
index 0000000..3803c66
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
@@ -0,0 +1,155 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+
+define float @i64tof32(i64 signext %a) {
+; MIPS32-LABEL: i64tof32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal __floatdisf
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i64 %a to float
+  ret float %conv
+}
+
+define float @i32tof32(i32 signext %a) {
+; MIPS32-LABEL: i32tof32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    mtc1 $4, $f0
+; MIPS32-NEXT:    cvt.s.w $f0, $f0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i32 %a to float
+  ret float %conv
+}
+
+define float @i16tof32(i16 signext %a) {
+; MIPS32-LABEL: i16tof32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sll $1, $4, 16
+; MIPS32-NEXT:    sra $1, $1, 16
+; MIPS32-NEXT:    mtc1 $1, $f0
+; MIPS32-NEXT:    cvt.s.w $f0, $f0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i16 %a to float
+  ret float %conv
+}
+
+define float @i8tof32(i8 signext %a) {
+; MIPS32-LABEL: i8tof32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sll $1, $4, 24
+; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    mtc1 $1, $f0
+; MIPS32-NEXT:    cvt.s.w $f0, $f0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i8 %a to float
+  ret float %conv
+}
+
+define double @i64tof64(i64 signext %a) {
+; MIPS32-LABEL: i64tof64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal __floatdidf
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i64 %a to double
+  ret double %conv
+}
+
+define double @i32tof64(i32 signext %a) {
+; MIPS32-LABEL: i32tof64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    mtc1 $4, $f0
+; MIPS32-NEXT:    cvt.d.w $f0, $f0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i32 %a to double
+  ret double %conv
+}
+
+define double @i16tof64(i16 signext %a) {
+; MIPS32-LABEL: i16tof64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sll $1, $4, 16
+; MIPS32-NEXT:    sra $1, $1, 16
+; MIPS32-NEXT:    mtc1 $1, $f0
+; MIPS32-NEXT:    cvt.d.w $f0, $f0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i16 %a to double
+  ret double %conv
+}
+
+define double @i8tof64(i8 signext %a) {
+; MIPS32-LABEL: i8tof64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sll $1, $4, 24
+; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    mtc1 $1, $f0
+; MIPS32-NEXT:    cvt.d.w $f0, $f0
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = sitofp i8 %a to double
+  ret double %conv
+}
+
+define float @u64tof32(i64 zeroext %a) {
+; MIPS32-LABEL: u64tof32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal __floatundisf
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = uitofp i64 %a to float
+  ret float %conv
+}
+
+define double @u64tof64(i64 zeroext %a) {
+; MIPS32-LABEL: u64tof64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal __floatundidf
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %conv = uitofp i64 %a to double
+  ret double %conv
+}

diff --git a/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir b/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
new file mode 100644 (file)
index 0000000..253e7d9
--- /dev/null
+++ b/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @i32tof32() {entry: ret void}
+  define void @i32tof64() {entry: ret void}
+
+...
+---
+name:            i32tof32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i32tof32
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; FP32: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
+    ; FP32: $f0 = COPY [[SITOFP]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: i32tof32
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; FP64: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
+    ; FP64: $f0 = COPY [[SITOFP]](s32)
+    ; FP64: RetRA implicit $f0
+    %0:_(s32) = COPY $a0
+    %1:_(s32) = G_SITOFP %0(s32)
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            i32tof64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; FP32-LABEL: name: i32tof64
+    ; FP32: liveins: $a0
+    ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; FP32: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s32)
+    ; FP32: $d0 = COPY [[SITOFP]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: i32tof64
+    ; FP64: liveins: $a0
+    ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+    ; FP64: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s32)
+    ; FP64: $d0 = COPY [[SITOFP]](s64)
+    ; FP64: RetRA implicit $d0
+    %0:_(s32) = COPY $a0
+    %1:_(s64) = G_SITOFP %0(s32)
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...