#define CPU_MMX (1UL<<13) /* MMX support required */
#define CPU_SSE (1UL<<14) /* Streaming SIMD extensions required */
#define CPU_SSE2 (1UL<<15) /* Streaming SIMD extensions 2 required */
-#define CPU_3DNow (1UL<<16) /* 3DNow! support required */
-#define CPU_Cyrix (1UL<<17) /* Cyrix-specific instruction */
-#define CPU_AMD (1UL<<18) /* AMD-specific inst. (older than K6) */
-#define CPU_SMM (1UL<<19) /* System Management Mode instruction */
-#define CPU_Prot (1UL<<20) /* Protected mode only instruction */
-#define CPU_Undoc (1UL<<21) /* Undocumented instruction */
-#define CPU_Obs (1UL<<22) /* Obsolete instruction */
-#define CPU_Priv (1UL<<23) /* Priveleged instruction */
+#define CPU_SSE3 (1UL<<16) /* Streaming SIMD extensions 3 required */
+#define CPU_3DNow (1UL<<17) /* 3DNow! support required */
+#define CPU_Cyrix (1UL<<18) /* Cyrix-specific instruction */
+#define CPU_AMD (1UL<<19) /* AMD-specific inst. (older than K6) */
+#define CPU_SMM (1UL<<20) /* System Management Mode instruction */
+#define CPU_Prot (1UL<<21) /* Protected mode only instruction */
+#define CPU_Undoc (1UL<<22) /* Undocumented instruction */
+#define CPU_Obs (1UL<<23) /* Obsolete instruction */
+#define CPU_Priv (1UL<<24) /* Priveleged instruction */
/* Technically not CPU capabilities, they do affect what instructions are
* available. These are tested against BITS==64.
*/
-#define CPU_64 (1UL<<24) /* Only available in 64-bit mode */
-#define CPU_Not64 (1UL<<25) /* Not available (invalid) in 64-bit mode */
+#define CPU_64 (1UL<<25) /* Only available in 64-bit mode */
+#define CPU_Not64 (1UL<<26) /* Not available (invalid) in 64-bit mode */
typedef struct yasm_arch_x86 {
yasm_arch_base arch; /* base structure */
{OPT_Mem|OPS_16|OPA_EA, 0, 0} },
{ CPU_FPU, MOD_SpAdd, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1,
{OPT_Mem|OPS_32|OPA_EA, 0, 0} },
- { CPU_FPU, MOD_Gap0|MOD_SpAdd, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1,
+ { CPU_FPU, MOD_Gap0|MOD_Op0Add|MOD_SpAdd, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1,
{OPT_Mem|OPS_64|OPA_EA, 0, 0} }
};
static const x86_insn_info fbldstp_insn[] = {
{OPT_SIMDReg|OPS_128|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} }
};
+/* SSE3 instructions */
+static const x86_insn_info lddqu_insn[] = {
+ { CPU_SSE3, 0, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0}, 0, 2,
+ {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_Mem|OPS_Any|OPA_EA, 0} }
+};
+
/* AMD 3DNow! instructions */
static const x86_insn_info now3d_insn[] = {
{ CPU_3DNow, MOD_Imm8, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2,
(A T H L O N "-"? "64") {
arch_x86->cpu_enabled =
CPU_186|CPU_286|CPU_386|CPU_486|CPU_586|CPU_686|CPU_K6|
- CPU_Athlon|CPU_Hammer|CPU_FPU|CPU_MMX|CPU_SSE|CPU_3DNow|
- CPU_SMM|CPU_Prot|CPU_Priv;
+ CPU_Athlon|CPU_Hammer|CPU_FPU|CPU_MMX|CPU_SSE|CPU_SSE2|
+ CPU_3DNow|CPU_SMM|CPU_Prot|CPU_Priv;
+ return;
+ }
+ P R E S C O T T {
+ arch_x86->cpu_enabled =
+ CPU_186|CPU_286|CPU_386|CPU_486|CPU_586|CPU_686|CPU_K6|
+ CPU_Athlon|CPU_Hammer|CPU_FPU|CPU_MMX|CPU_SSE|CPU_SSE2|
+ CPU_SSE3|CPU_3DNow|CPU_SMM|CPU_Prot|CPU_Priv;
return;
}
N O S S E { arch_x86->cpu_enabled &= ~CPU_SSE; return; }
S S E "2" { arch_x86->cpu_enabled |= CPU_SSE2; return; }
N O S S E "2" { arch_x86->cpu_enabled &= ~CPU_SSE2; return; }
+ S S E "3" { arch_x86->cpu_enabled |= CPU_SSE3; return; }
+ N O S S E "3" { arch_x86->cpu_enabled &= ~CPU_SSE3; return; }
+ P N I { arch_x86->cpu_enabled |= CPU_SSE3; return; }
+ N O P N I { arch_x86->cpu_enabled &= ~CPU_SSE3; return; }
"3" D N O W { arch_x86->cpu_enabled |= CPU_3DNow; return; }
N O "3" D N O W { arch_x86->cpu_enabled &= ~CPU_3DNow; return; }
C Y R I X { arch_x86->cpu_enabled |= CPU_Cyrix; return; }
V E R W { RET_INSN(prot286, 0x0500, CPU_286|CPU_Prot); }
/* Floating point instructions */
F L D { RET_INSN(fldstp, 0x0500C0, CPU_FPU); }
- F I L D { RET_INSN(fildstp, 0x0500, CPU_FPU); }
+ F I L D { RET_INSN(fildstp, 0x050200, CPU_FPU); }
F B L D { RET_INSN(fbldstp, 0x04, CPU_FPU); }
F S T { RET_INSN(fst, 0, CPU_FPU); }
F I S T { RET_INSN(fiarith, 0x02DB, CPU_FPU); }
F S T P { RET_INSN(fldstp, 0x0703D8, CPU_FPU); }
- F I S T P { RET_INSN(fildstp, 0x0703, CPU_FPU); }
+ F I S T P { RET_INSN(fildstp, 0x070203, CPU_FPU); }
F B S T P { RET_INSN(fbldstp, 0x06, CPU_FPU); }
F X C H { RET_INSN(fxch, 0, CPU_FPU); }
F C O M { RET_INSN(fcom, 0x02D0, CPU_FPU); }
P S R L D Q { RET_INSN(pslrldq, 0x03, CPU_SSE2); }
P U N P C K H Q D Q { RET_INSN(ssess, 0x666D, CPU_SSE2); }
P U N P C K L Q D Q { RET_INSN(ssess, 0x666C, CPU_SSE2); }
+ /* SSE3 / PNI (Prescott New Instructions) instructions */
+ A D D S U B P D { RET_INSN(ssess, 0x66D0, CPU_SSE3); }
+ A D D S U B P S { RET_INSN(ssess, 0xF2D0, CPU_SSE3); }
+ F I S T T P { RET_INSN(fildstp, 0x010001, CPU_SSE3); }
+ H A D D P D { RET_INSN(ssess, 0x667C, CPU_SSE3); }
+ H A D D P S { RET_INSN(ssess, 0xF27C, CPU_SSE3); }
+ H S U B P D { RET_INSN(ssess, 0x667D, CPU_SSE3); }
+ H S U B P S { RET_INSN(ssess, 0xF27D, CPU_SSE3); }
+ L D D Q U { RET_INSN(lddqu, 0, CPU_SSE3); }
+ M O N I T O R { RET_INSN(threebyte, 0x0F01C8, CPU_SSE3); }
+ M O V D D U P { RET_INSN(cvt_xmm_xmm64_ss, 0xF212, CPU_SSE3); }
+ M O V S H D U P { RET_INSN(ssess, 0xF316, CPU_SSE3); }
+ M O V S L D U P { RET_INSN(ssess, 0xF312, CPU_SSE3); }
+ M W A I T { RET_INSN(threebyte, 0x0F01C9, CPU_SSE3); }
/* AMD 3DNow! instructions */
P R E F E T C H { RET_INSN(twobytemem, 0x000F0D, CPU_3DNow); }
P R E F E T C H W { RET_INSN(twobytemem, 0x010F0D, CPU_3DNow); }
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