[X86] If we see an insert of a bitcast into zero vector, canonicalize it to move...

This improves detection of zeroing of upper bits during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315161 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 7305af6b39dfbf7eccab4b371802b9cd051e188f..28a30d7824ac099cab6d7caefdfd4a758269cba7 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -36107,6 +36107,20 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG,
                          SubVec.getOperand(1),
                          DAG.getIntPtrConstant(IdxVal + Idx2Val, dl));
     }
+
+    // If we're inserting a bitcast into zeros, rewrite the insert and move the
+    // bitcast to the other side. This helps with detecting zero extending
+    // during isel.
+    // TODO: Is this useful for other indices than 0?
+    if (SubVec.getOpcode() == ISD::BITCAST && IdxVal == 0) {
+      MVT CastVT = SubVec.getOperand(0).getSimpleValueType();
+      unsigned NumElems = OpVT.getSizeInBits() / CastVT.getScalarSizeInBits();
+      MVT NewVT = MVT::getVectorVT(CastVT.getVectorElementType(), NumElems);
+      SDValue Insert = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
+                                   DAG.getBitcast(NewVT, Vec),
+                                   SubVec.getOperand(0), N->getOperand(2));
+      return DAG.getBitcast(OpVT, Insert);
+    }
   }
 
   // If this is an insert of an extract, combine to a shuffle. Don't do this

diff --git a/lib/Target/X86/X86InstrVecCompiler.td b/lib/Target/X86/X86InstrVecCompiler.td
index f6b41c46f6d8d00a84313fd25999359d15d45f54..7e2195cf93aa8b18ab3bce0ca38eaa5a8a77f47b 100644 (file)
--- a/lib/Target/X86/X86InstrVecCompiler.td
+++ b/lib/Target/X86/X86InstrVecCompiler.td
@@ -368,7 +368,8 @@ let Predicates = [HasAVX512, NoVLX] in {
 // where we explicitly insert zeros.
 class veczeroupper<ValueType vt, RegisterClass RC> :
   PatLeaf<(vt RC:$src), [{
-    return N->getOpcode() == X86ISD::VPMADDWD;
+    return N->getOpcode() == X86ISD::VPMADDWD ||
+           N->getOpcode() == X86ISD::PSADBW;
   }]>;
 
 def zeroupperv2f64 : veczeroupper<v2f64, VR128>;

diff --git a/test/CodeGen/X86/sad.ll b/test/CodeGen/X86/sad.ll
index e8a55215dc8d5a3c6edf2fadefbf2d09173c1cd4..27a220e7cd6b59ad8c64d76686a8dcc2ee8975c2 100644 (file)
--- a/test/CodeGen/X86/sad.ll
+++ b/test/CodeGen/X86/sad.ll
@@ -43,7 +43,6 @@ define i32 @sad_16i8() nounwind {
 ; AVX2-NEXT:    # =>This Inner Loop Header: Depth=1
 ; AVX2-NEXT:    vmovdqu a+1024(%rax), %xmm2
 ; AVX2-NEXT:    vpsadbw b+1024(%rax), %xmm2, %xmm2
-; AVX2-NEXT:    vmovdqa %xmm2, %xmm2
 ; AVX2-NEXT:    vpaddd %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    addq $4, %rax
 ; AVX2-NEXT:    jne .LBB0_1
@@ -67,7 +66,6 @@ define i32 @sad_16i8() nounwind {
 ; AVX512F-NEXT:    # =>This Inner Loop Header: Depth=1
 ; AVX512F-NEXT:    vmovdqu a+1024(%rax), %xmm1
 ; AVX512F-NEXT:    vpsadbw b+1024(%rax), %xmm1, %xmm1
-; AVX512F-NEXT:    vmovdqa %xmm1, %xmm1
 ; AVX512F-NEXT:    vpaddd %zmm0, %zmm1, %zmm0
 ; AVX512F-NEXT:    addq $4, %rax
 ; AVX512F-NEXT:    jne .LBB0_1
@@ -93,7 +91,6 @@ define i32 @sad_16i8() nounwind {
 ; AVX512BW-NEXT:    # =>This Inner Loop Header: Depth=1
 ; AVX512BW-NEXT:    vmovdqu a+1024(%rax), %xmm1
 ; AVX512BW-NEXT:    vpsadbw b+1024(%rax), %xmm1, %xmm1
-; AVX512BW-NEXT:    vmovdqa %xmm1, %xmm1
 ; AVX512BW-NEXT:    vpaddd %zmm0, %zmm1, %zmm0
 ; AVX512BW-NEXT:    addq $4, %rax
 ; AVX512BW-NEXT:    jne .LBB0_1
@@ -315,7 +312,6 @@ define i32 @sad_32i8() nounwind {
 ; AVX512F-NEXT:    # =>This Inner Loop Header: Depth=1
 ; AVX512F-NEXT:    vmovdqa a+1024(%rax), %ymm2
 ; AVX512F-NEXT:    vpsadbw b+1024(%rax), %ymm2, %ymm2
-; AVX512F-NEXT:    vmovdqa %ymm2, %ymm2
 ; AVX512F-NEXT:    vpaddd %zmm1, %zmm2, %zmm1
 ; AVX512F-NEXT:    addq $4, %rax
 ; AVX512F-NEXT:    jne .LBB1_1
@@ -343,7 +339,6 @@ define i32 @sad_32i8() nounwind {
 ; AVX512BW-NEXT:    # =>This Inner Loop Header: Depth=1
 ; AVX512BW-NEXT:    vmovdqa a+1024(%rax), %ymm2
 ; AVX512BW-NEXT:    vpsadbw b+1024(%rax), %ymm2, %ymm2
-; AVX512BW-NEXT:    vmovdqa %ymm2, %ymm2
 ; AVX512BW-NEXT:    vpaddd %zmm1, %zmm2, %zmm1
 ; AVX512BW-NEXT:    addq $4, %rax
 ; AVX512BW-NEXT:    jne .LBB1_1