[AArch64] Preserve register flags when promoting a load from store.

Summary:
This patch updates promoteLoadFromStore to use the store MachineOperand as the
source operand of the of the new instruction instead of creating a new
register MachineOperand. This way, the existing register flags are
preserved.

This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468).

Reviewers: MatzeB, t.p.northover, junbuml

Reviewed By: MatzeB

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34402

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305885 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 9243eb91cc1ac708adc3c24619e7a4ac6adb7484..c35de77727e57526d102e3eea9a6dd1dbb0c1392 100644 (file)
--- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -795,6 +795,7 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
   int LoadSize = getMemScale(*LoadI);
   int StoreSize = getMemScale(*StoreI);
   unsigned LdRt = getLdStRegOp(*LoadI).getReg();
+  const MachineOperand &StMO = getLdStRegOp(*StoreI);
   unsigned StRt = getLdStRegOp(*StoreI).getReg();
   bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
 
@@ -819,7 +820,7 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
         BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
                 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
             .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
-            .addReg(StRt)
+            .add(StMO)
             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
   } else {
     // FIXME: Currently we disable this transformation in big-endian targets as
@@ -860,14 +861,14 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
           BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
                   TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
                   DestReg)
-              .addReg(StRt)
+              .add(StMO)
               .addImm(AndMaskEncoded);
     } else {
       BitExtMI =
           BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
                   TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
                   DestReg)
-              .addReg(StRt)
+              .add(StMO)
               .addImm(Immr)
               .addImm(Imms);
     }

diff --git a/test/CodeGen/AArch64/ldst-opt.mir b/test/CodeGen/AArch64/ldst-opt.mir
index f7641d3ffd04cdbb5d3a14d8b7eda5edf7ff253b..5b3576d898e47026987317d2cd1c0c651cb1a048 100644 (file)
--- a/test/CodeGen/AArch64/ldst-opt.mir
+++ b/test/CodeGen/AArch64/ldst-opt.mir
@@ -34,7 +34,7 @@ body: |
 # Don't count transient instructions towards search limits.
 # CHECK-LABEL: name: promote-load-from-store
 # CHECK: STRWui %w1
-# CHECK: UBFMWri %w1
+# CHECK: UBFMWri killed %w1
 ---
 name: store-pair
 tracksRegLiveness: true
@@ -144,3 +144,21 @@ body: |
 # CHECK: %wzr = COPY %w1
 # CHECK: %w11 = ORRWrs %wzr, %w1, 0
 # CHECK: HINT 0, implicit %w11
+---
+name: promote-load-from-store-undef
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: %x0, %x2, %lr
+
+    STRWui undef %w1, %x0, 0 :: (store 4)
+    %w0 = LDRBBui %x0, 1 :: (load 2)
+    STRHHui undef %w3, %x2, 0 :: (store 4)
+    %w1 = LDRBBui %x2, 0 :: (load 4)
+    RET %lr, implicit %w0
+...
+# CHECK-LABEL: name: promote-load-from-store-undef
+# CHECK: STRWui undef %w1
+# CHECK: UBFMWri undef %w1
+# CHECK: STRHHui undef %w3
+# CHECK: ANDWri undef %w3