]> granicus.if.org Git - llvm/commitdiff
Remove subtarget dependence in pass pipeline setup for AArch64.
authorEric Christopher <echristo@gmail.com>
Tue, 3 Mar 2015 23:22:40 +0000 (23:22 +0000)
committerEric Christopher <echristo@gmail.com>
Tue, 3 Mar 2015 23:22:40 +0000 (23:22 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231165 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
lib/Target/AArch64/AArch64TargetMachine.cpp

index 7f1e3495775c3699b55b51231ca542b31865c83c..9ad46736a305cfa048cbaf1971b6027fa8a820ab 100644 (file)
@@ -307,6 +307,11 @@ public:
 //===----------------------------------------------------------------------===//
 
 bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
+  // Don't do anything if this isn't an A53 or A57.
+  if (!(F.getSubtarget<AArch64Subtarget>().isCortexA53() ||
+        F.getSubtarget<AArch64Subtarget>().isCortexA57()))
+    return false;
+
   bool Changed = false;
   DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n");
 
index d73d0b3f8b709473f2bd8d8e08ef4e5175710417..4389cfad80db32f4ec9f7cb1b2f3c69fc7b6a473 100644 (file)
@@ -287,10 +287,7 @@ void AArch64PassConfig::addPostRegAlloc() {
   // Change dead register definitions to refer to the zero register.
   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
     addPass(createAArch64DeadRegisterDefinitions());
-  if (TM->getOptLevel() != CodeGenOpt::None &&
-      (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
-       TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
-      usingDefaultRegAlloc())
+  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
     // Improve performance for some FP/SIMD code for A57.
     addPass(createAArch64A57FPLoadBalancing());
 }