Merging r339533:

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r339533 | ctopper | 2018-08-13 07:26:49 +0200 (Mon, 13 Aug 2018) | 5 lines

[SelectionDAG] In PromoteFloatRes_BITCAST, insert a bitcast before the fp16_to_fp in case the input type isn't an i16.

The bitcast can be further legalized as needed.

Fixes PR38533.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@339855 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 9aa0ea15f3b790e34555be3a78ce25323c0269b4..feca1c10f52b02a9f3c4e96f78b7bc0748aa3fa9 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1941,8 +1941,10 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
   EVT VT = N->getValueType(0);
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
-  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT,
-                     N->getOperand(0));
+  // Input type isn't guaranteed to be i16 so bitcast if not. The bitcast
+  // will be legalized further if necessary.
+  SDValue Cast = DAG.getBitcast(MVT::i16, N->getOperand(0));
+  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, Cast);
 }
 
 SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {

diff --git a/test/CodeGen/X86/pr38533.ll b/test/CodeGen/X86/pr38533.ll
new file mode 100644 (file)
index 0000000..4c57d84
--- /dev/null
+++ b/test/CodeGen/X86/pr38533.ll
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+define void @constant_fold_vector_to_half() {
+; CHECK-LABEL: constant_fold_vector_to_half:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movw $16384, (%rax) # imm = 0x4000
+; CHECK-NEXT:    retq
+  store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef
+  ret void
+}