* x86id.re: Unbreak movq for NASM parser. I accidentally overrode it when

defining the mov forms for GAS.  While I'm here, fix movq so it also
supports the 64-bit move registers (per Intel's spec, AMD has it under movd)
and copy the MMX/SSE2 versions of movq into mov so they're visible to the
GAS parser (and only the GAS parser).

Add a whole bunch of testcases to test movd and movq in both 32 bit and 64
bit modes for both GAS and NASM parsers.

svn path=/trunk/yasm/; revision=1255

diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc
index 61de85e821fbbd7afb75201812a6e58112b42dba..64a1b84f4daa4659e0bad6029fbf147bafd0b52a 100644 (file)
--- a/modules/arch/x86/tests/Makefile.inc
+++ b/modules/arch/x86/tests/Makefile.inc
@@ -85,6 +85,12 @@ EXTRA_DIST += modules/arch/x86/tests/mem64hi32.hex
 EXTRA_DIST += modules/arch/x86/tests/mem64rip.asm
 EXTRA_DIST += modules/arch/x86/tests/mem64rip.errwarn
 EXTRA_DIST += modules/arch/x86/tests/mem64rip.hex
+EXTRA_DIST += modules/arch/x86/tests/movdq32.asm
+EXTRA_DIST += modules/arch/x86/tests/movdq32.errwarn
+EXTRA_DIST += modules/arch/x86/tests/movdq32.hex
+EXTRA_DIST += modules/arch/x86/tests/movdq64.asm
+EXTRA_DIST += modules/arch/x86/tests/movdq64.errwarn
+EXTRA_DIST += modules/arch/x86/tests/movdq64.hex
 EXTRA_DIST += modules/arch/x86/tests/negequ.asm
 EXTRA_DIST += modules/arch/x86/tests/negequ.errwarn
 EXTRA_DIST += modules/arch/x86/tests/negequ.hex
@@ -160,6 +166,8 @@ EXTRA_DIST += modules/arch/x86/tests/xmm64.asm
 EXTRA_DIST += modules/arch/x86/tests/xmm64.errwarn
 EXTRA_DIST += modules/arch/x86/tests/xmm64.hex
 
+EXTRA_DIST += modules/arch/x86/tests/gas32/Makefile.inc
 EXTRA_DIST += modules/arch/x86/tests/gas64/Makefile.inc
 
+include modules/arch/x86/tests/gas32/Makefile.inc
 include modules/arch/x86/tests/gas64/Makefile.inc

diff --git a/modules/arch/x86/tests/gas32/Makefile.inc b/modules/arch/x86/tests/gas32/Makefile.inc
new file mode 100644 (file)
index 0000000..4fa0730
--- /dev/null
+++ b/modules/arch/x86/tests/gas32/Makefile.inc
@@ -0,0 +1,9 @@
+# $Id$
+
+TESTS += modules/arch/x86/tests/gas32/x86_gas32_test.sh
+
+EXTRA_DIST += modules/arch/x86/tests/gas32/x86_gas32_test.sh
+EXTRA_DIST += modules/arch/x86/tests/gas32/gas-movdq32.asm
+EXTRA_DIST += modules/arch/x86/tests/gas32/gas-movdq32.errwarn
+EXTRA_DIST += modules/arch/x86/tests/gas32/gas-movdq32.hex
+

diff --git a/modules/arch/x86/tests/gas32/gas-movdq32.asm b/modules/arch/x86/tests/gas32/gas-movdq32.asm
new file mode 100644 (file)
index 0000000..a90c1a6
--- /dev/null
+++ b/modules/arch/x86/tests/gas32/gas-movdq32.asm
@@ -0,0 +1,20 @@
+movd %mm0, %eax
+movd %eax, %mm0
+movd %mm0, 0
+movd 0, %mm(0)
+
+movd %xmm0, %eax
+movd %eax, %xmm0
+movd %xmm0, 0
+movd 0, %xmm0
+
+movq %xmm0, 0
+movq 0, %xmm0
+movq %xmm1, %xmm0
+movq %xmm0, %xmm1
+
+movq %mm0, 0
+movq 0, %mm0
+movq %mm1, %mm0
+movq %mm0, %mm1
+

diff --git a/modules/arch/x86/tests/gas32/gas-movdq32.errwarn b/modules/arch/x86/tests/gas32/gas-movdq32.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/modules/arch/x86/tests/gas32/gas-movdq32.hex b/modules/arch/x86/tests/gas32/gas-movdq32.hex
new file mode 100644 (file)
index 0000000..6683682
--- /dev/null
+++ b/modules/arch/x86/tests/gas32/gas-movdq32.hex
@@ -0,0 +1,440 @@
+7f 
+45 
+4c 
+46 
+01 
+01 
+01 
+00 
+00 
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diff --git a/modules/arch/x86/tests/gas32/x86_gas32_test.sh b/modules/arch/x86/tests/gas32/x86_gas32_test.sh
new file mode 100755 (executable)
index 0000000..af84899
--- /dev/null
+++ b/modules/arch/x86/tests/gas32/x86_gas32_test.sh
@@ -0,0 +1,4 @@
+#! /bin/sh
+# $Id$
+${srcdir}/out_test.sh x86_gas32_test modules/arch/x86/tests/gas32 "x86 gas format" "-f elf32 -p gas" ".o"
+exit $?

diff --git a/modules/arch/x86/tests/gas64/Makefile.inc b/modules/arch/x86/tests/gas64/Makefile.inc
index 405b021477d42dc4fd0844934ab3ea0ad4794ac5..050d1f75791fba89083f07c8c166d0dfdd47787b 100644 (file)
--- a/modules/arch/x86/tests/gas64/Makefile.inc
+++ b/modules/arch/x86/tests/gas64/Makefile.inc
@@ -12,6 +12,9 @@ EXTRA_DIST += modules/arch/x86/tests/gas64/gas-fp.hex
 EXTRA_DIST += modules/arch/x86/tests/gas64/gas-inout.asm
 EXTRA_DIST += modules/arch/x86/tests/gas64/gas-inout.errwarn
 EXTRA_DIST += modules/arch/x86/tests/gas64/gas-inout.hex
+EXTRA_DIST += modules/arch/x86/tests/gas64/gas-movdq64.asm
+EXTRA_DIST += modules/arch/x86/tests/gas64/gas-movdq64.errwarn
+EXTRA_DIST += modules/arch/x86/tests/gas64/gas-movdq64.hex
 EXTRA_DIST += modules/arch/x86/tests/gas64/gas-movsxs.asm
 EXTRA_DIST += modules/arch/x86/tests/gas64/gas-movsxs.errwarn
 EXTRA_DIST += modules/arch/x86/tests/gas64/gas-movsxs.hex

diff --git a/modules/arch/x86/tests/gas64/gas-movdq64.asm b/modules/arch/x86/tests/gas64/gas-movdq64.asm
new file mode 100644 (file)
index 0000000..657114b
--- /dev/null
+++ b/modules/arch/x86/tests/gas64/gas-movdq64.asm
@@ -0,0 +1,30 @@
+movd %mm(0), %eax
+movd %eax, %mm(0)
+movd %mm(0), %rax
+movd %rax, %mm(0)
+movd %mm(0), 0
+movd 0, %mm(0)
+
+movd %xmm(0), %eax
+movd %eax, %xmm(0)
+movd %xmm(0), %rax
+movd %rax, %xmm(0)
+movd %xmm(0), 0
+movd 0, %xmm(0)
+
+movq %xmm(0), 0
+movq 0, %xmm(0)
+movq %xmm(1), %xmm(0)
+movq %xmm(0), %xmm(1)
+
+movq %mm(0), 0
+movq 0, %mm(0)
+movq %mm(1), %mm(0)
+movq %mm(0), %mm(1)
+
+movq %xmm(0), %rax
+movq %rax, %xmm(0)
+
+movq %mm(0), %rax
+movq %rax, %mm(0)
+

diff --git a/modules/arch/x86/tests/gas64/gas-movdq64.errwarn b/modules/arch/x86/tests/gas64/gas-movdq64.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/modules/arch/x86/tests/gas64/gas-movdq64.hex b/modules/arch/x86/tests/gas64/gas-movdq64.hex
new file mode 100644 (file)
index 0000000..5128928
--- /dev/null
+++ b/modules/arch/x86/tests/gas64/gas-movdq64.hex
@@ -0,0 +1,640 @@
+7f 
+45 
+4c 
+46 
+02 
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diff --git a/modules/arch/x86/tests/movdq32.asm b/modules/arch/x86/tests/movdq32.asm
new file mode 100644 (file)
index 0000000..c000e58
--- /dev/null
+++ b/modules/arch/x86/tests/movdq32.asm
@@ -0,0 +1,21 @@
+[bits 32]
+movd eax, mm0
+movd mm0, eax
+movd [0], mm0
+movd mm0, [0]
+
+movd eax, xmm0
+movd xmm0, eax
+movd [0], xmm0
+movd xmm0, [0]
+
+movq [0], xmm0
+movq xmm0, [0]
+movq xmm0, xmm1
+movq xmm1, xmm0
+
+movq [0], mm0
+movq mm0, [0]
+movq mm0, mm1
+movq mm1, mm0
+

diff --git a/modules/arch/x86/tests/movdq32.errwarn b/modules/arch/x86/tests/movdq32.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/modules/arch/x86/tests/movdq32.hex b/modules/arch/x86/tests/movdq32.hex
new file mode 100644 (file)
index 0000000..6fea672
--- /dev/null
+++ b/modules/arch/x86/tests/movdq32.hex
@@ -0,0 +1,88 @@
+0f 
+7e 
+c0 
+0f 
+6e 
+c0 
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+7e 
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+00 
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+0f 
+6f 
+c1 
+0f 
+6f 
+c8 

diff --git a/modules/arch/x86/tests/movdq64.asm b/modules/arch/x86/tests/movdq64.asm
new file mode 100644 (file)
index 0000000..ba36717
--- /dev/null
+++ b/modules/arch/x86/tests/movdq64.asm
@@ -0,0 +1,31 @@
+[bits 64]
+movd eax, mm0
+movd mm0, eax
+movd rax, mm0
+movd mm0, rax
+movd [0], mm0
+movd mm0, [0]
+
+movd eax, xmm0
+movd xmm0, eax
+movd rax, xmm0
+movd xmm0, rax
+movd [0], xmm0
+movd xmm0, [0]
+
+movq [0], xmm0
+movq xmm0, [0]
+movq xmm0, xmm1
+movq xmm1, xmm0
+
+movq [0], mm0
+movq mm0, [0]
+movq mm0, mm1
+movq mm1, mm0
+
+movq rax, xmm0
+movq xmm0, rax
+
+movq rax, mm0
+movq mm0, rax
+

diff --git a/modules/arch/x86/tests/movdq64.errwarn b/modules/arch/x86/tests/movdq64.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/modules/arch/x86/tests/movdq64.hex b/modules/arch/x86/tests/movdq64.hex
new file mode 100644 (file)
index 0000000..d80f0c2
--- /dev/null
+++ b/modules/arch/x86/tests/movdq64.hex
@@ -0,0 +1,132 @@
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diff --git a/modules/arch/x86/x86id.re b/modules/arch/x86/x86id.re
index 23d4934c82497da94254f29d27478ca28c3748b7..6d23d343999ee4a7605e8d4514c831c1d2fc4d89 100644 (file)
--- a/modules/arch/x86/x86id.re
+++ b/modules/arch/x86/x86id.re
@@ -506,7 +506,35 @@ static const x86_insn_info mov_insn[] = {
     { CPU_386|CPU_Priv|CPU_Not64, MOD_GasSufL, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0,
       2, {OPT_Reg|OPS_32|OPA_EA, OPT_DRReg|OPS_32|OPA_Spare, 0} },
     { CPU_Hammer|CPU_Priv|CPU_64, MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0,
-      2, {OPT_Reg|OPS_64|OPA_EA, OPT_DRReg|OPS_32|OPA_Spare, 0} }
+      2, {OPT_Reg|OPS_64|OPA_EA, OPT_DRReg|OPS_32|OPA_Spare, 0} },
+
+    /* MMX/SSE2 forms for GAS parser (copied from movq_insn) */
+    { CPU_MMX, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    },
+    { CPU_MMX|CPU_Hammer|CPU_64, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0, 2,
+      {0x0F, 0x6E, 0}, 0, 2,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_MMX, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2,
+      {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0}
+    },
+    { CPU_MMX|CPU_Hammer|CPU_64, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0, 2,
+      {0x0F, 0x7E, 0}, 0, 2,
+      {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
+    { CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
+    { CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0}
+    },
+    { CPU_SSE2|CPU_Hammer|CPU_64, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0x66, 2,
+      {0x0F, 0x6E, 0}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
+    { CPU_SSE2, MOD_GasOnly|MOD_GasSufQ, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2,
+      {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0}
+    },
+    { CPU_SSE2|CPU_Hammer|CPU_64, MOD_GasOnly|MOD_GasSufQ, 64, 0, 0x66, 2,
+      {0x0F, 0x7E, 0}, 0, 2,
+      {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
 };
 
 /* 64-bit absolute move (for GAS).
@@ -1534,17 +1562,25 @@ static const x86_insn_info movq_insn[] = {
     { CPU_MMX, 0, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2,
       {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0}
     },
+    { CPU_MMX|CPU_Hammer|CPU_64, 0, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2,
+      {OPT_SIMDReg|OPS_64|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
     { CPU_MMX, 0, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2,
       {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0}
     },
+    { CPU_MMX|CPU_Hammer|CPU_64, 0, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2,
+      {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_64|OPA_Spare, 0} },
     { CPU_SSE2, 0, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2,
       {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDReg|OPS_128|OPA_EA, 0} },
     { CPU_SSE2, 0, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2,
       {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, 0}
     },
+    { CPU_SSE2|CPU_Hammer|CPU_64, 0, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2,
+      {OPT_SIMDReg|OPS_128|OPA_Spare, OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, 0} },
     { CPU_SSE2, 0, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2,
       {OPT_SIMDRM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0}
-    }
+    },
+    { CPU_SSE2|CPU_Hammer|CPU_64, 0, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2,
+      {OPT_RM|OPS_64|OPS_Relaxed|OPA_EA, OPT_SIMDReg|OPS_128|OPA_Spare, 0} }
 };
 static const x86_insn_info mmxsse2_insn[] = {
     { CPU_MMX, MOD_Op1Add, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2,
@@ -3439,7 +3475,7 @@ yasm_x86__parse_check_insn(yasm_arch *arch, unsigned long data[4],
        /* instructions */
 
        /* Move */
-       M O V [bBwWlLqQ]? { RET_INSN(3, mov, 0, CPU_Any); }
+       M O V [bBwWlL]? { RET_INSN(3, mov, 0, CPU_Any); }
        M O V A B S [bBwWlLqQ]? { RET_INSN_GAS(6, movabs, 0, CPU_Hammer|CPU_64); }
        /* Move with sign/zero extend */
        M O V S B [wWlL] { suffix_ofs = -2; RET_INSN_GAS(4, movszx, 0xBE, CPU_386); }
@@ -4002,7 +4038,12 @@ yasm_x86__parse_check_insn(yasm_arch *arch, unsigned long data[4],
        /* MMX/SSE2 instructions */
        E M M S { RET_INSN(4, twobyte, 0x0F77, CPU_MMX); }
        M O V D { RET_INSN(4, movd, 0, CPU_MMX); }
-       M O V Q { RET_INSN(4, movq, 0, CPU_MMX); }
+       M O V Q {
+           if (arch_x86->parser == X86_PARSER_GAS)
+               RET_INSN(3, mov, 0, CPU_Any);
+           else
+               RET_INSN(4, movq, 0, CPU_MMX);
+       }
        P A C K S S D W { RET_INSN(8, mmxsse2, 0x6B, CPU_MMX); }
        P A C K S S W B { RET_INSN(8, mmxsse2, 0x63, CPU_MMX); }
        P A C K U S W B { RET_INSN(8, mmxsse2, 0x67, CPU_MMX); }