SystemZCallingConv.cpp
SystemZConstantPoolValue.cpp
SystemZElimCompare.cpp
- SystemZExpandPseudo.cpp
SystemZFrameLowering.cpp
SystemZHazardRecognizer.cpp
SystemZISelDAGToDAG.cpp
FunctionPass *createSystemZISelDag(SystemZTargetMachine &TM,
CodeGenOpt::Level OptLevel);
FunctionPass *createSystemZElimComparePass(SystemZTargetMachine &TM);
-FunctionPass *createSystemZExpandPseudoPass(SystemZTargetMachine &TM);
FunctionPass *createSystemZShortenInstPass(SystemZTargetMachine &TM);
FunctionPass *createSystemZLongBranchPass(SystemZTargetMachine &TM);
FunctionPass *createSystemZLDCleanupPass(SystemZTargetMachine &TM);
+++ /dev/null
-//==-- SystemZExpandPseudo.cpp - Expand pseudo instructions -------*- C++ -*-=//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a pass that expands pseudo instructions into target
-// instructions to allow proper scheduling and other late optimizations. This
-// pass should be run after register allocation but before the post-regalloc
-// scheduling pass.
-//
-//===----------------------------------------------------------------------===//
-
-#include "SystemZ.h"
-#include "SystemZInstrInfo.h"
-#include "SystemZSubtarget.h"
-#include "llvm/CodeGen/LivePhysRegs.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-using namespace llvm;
-
-#define SYSTEMZ_EXPAND_PSEUDO_NAME "SystemZ pseudo instruction expansion pass"
-
-namespace llvm {
- void initializeSystemZExpandPseudoPass(PassRegistry&);
-}
-
-namespace {
-class SystemZExpandPseudo : public MachineFunctionPass {
-public:
- static char ID;
- SystemZExpandPseudo() : MachineFunctionPass(ID) {
- initializeSystemZExpandPseudoPass(*PassRegistry::getPassRegistry());
- }
-
- const SystemZInstrInfo *TII;
-
- bool runOnMachineFunction(MachineFunction &Fn) override;
-
- StringRef getPassName() const override { return SYSTEMZ_EXPAND_PSEUDO_NAME; }
-
-private:
- bool expandMBB(MachineBasicBlock &MBB);
- bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
- bool expandLOCRMux(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI);
-};
-char SystemZExpandPseudo::ID = 0;
-}
-
-INITIALIZE_PASS(SystemZExpandPseudo, "systemz-expand-pseudo",
- SYSTEMZ_EXPAND_PSEUDO_NAME, false, false)
-
-/// Returns an instance of the pseudo instruction expansion pass.
-FunctionPass *llvm::createSystemZExpandPseudoPass(SystemZTargetMachine &TM) {
- return new SystemZExpandPseudo();
-}
-
-// MI is a load-register-on-condition pseudo instruction that could not be
-// handled as a single hardware instruction. Replace it by a branch sequence.
-bool SystemZExpandPseudo::expandLOCRMux(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- MachineFunction &MF = *MBB.getParent();
- const BasicBlock *BB = MBB.getBasicBlock();
- MachineInstr &MI = *MBBI;
- DebugLoc DL = MI.getDebugLoc();
- Register DestReg = MI.getOperand(0).getReg();
- Register SrcReg = MI.getOperand(2).getReg();
- unsigned CCValid = MI.getOperand(3).getImm();
- unsigned CCMask = MI.getOperand(4).getImm();
-
- LivePhysRegs LiveRegs(TII->getRegisterInfo());
- LiveRegs.addLiveOuts(MBB);
- for (auto I = std::prev(MBB.end()); I != MBBI; --I)
- LiveRegs.stepBackward(*I);
-
- // Splice MBB at MI, moving the rest of the block into RestMBB.
- MachineBasicBlock *RestMBB = MF.CreateMachineBasicBlock(BB);
- MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
- RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
- RestMBB->transferSuccessors(&MBB);
- for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
- RestMBB->addLiveIn(*I);
-
- // Create a new block MoveMBB to hold the move instruction.
- MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
- MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
- MoveMBB->addLiveIn(SrcReg);
- for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
- MoveMBB->addLiveIn(*I);
-
- // At the end of MBB, create a conditional branch to RestMBB if the
- // condition is false, otherwise fall through to MoveMBB.
- BuildMI(&MBB, DL, TII->get(SystemZ::BRC))
- .addImm(CCValid).addImm(CCMask ^ CCValid).addMBB(RestMBB);
- MBB.addSuccessor(RestMBB);
- MBB.addSuccessor(MoveMBB);
-
- // In MoveMBB, emit an instruction to move SrcReg into DestReg,
- // then fall through to RestMBB.
- TII->copyPhysReg(*MoveMBB, MoveMBB->end(), DL, DestReg, SrcReg,
- MI.getOperand(2).isKill());
- MoveMBB->addSuccessor(RestMBB);
-
- NextMBBI = MBB.end();
- MI.eraseFromParent();
- return true;
-}
-
-/// If MBBI references a pseudo instruction that should be expanded here,
-/// do the expansion and return true. Otherwise return false.
-bool SystemZExpandPseudo::expandMI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
- MachineInstr &MI = *MBBI;
- switch (MI.getOpcode()) {
- case SystemZ::LOCRMux:
- return expandLOCRMux(MBB, MBBI, NextMBBI);
- default:
- break;
- }
- return false;
-}
-
-/// Iterate over the instructions in basic block MBB and expand any
-/// pseudo instructions. Return true if anything was modified.
-bool SystemZExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
- bool Modified = false;
-
- MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
- while (MBBI != E) {
- MachineBasicBlock::iterator NMBBI = std::next(MBBI);
- Modified |= expandMI(MBB, MBBI, NMBBI);
- MBBI = NMBBI;
- }
-
- return Modified;
-}
-
-bool SystemZExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
- TII = static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
-
- bool Modified = false;
- for (auto &MBB : MF)
- Modified |= expandMBB(MBB);
- return Modified;
-}
-
#include "SystemZGenInstrInfo.inc"
#define DEBUG_TYPE "systemz-II"
-STATISTIC(LOCRMuxJumps, "Number of LOCRMux jump-sequences (lower is better)");
// Return a mask with Count low bits set.
static uint64_t allOnes(unsigned int Count) {
return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
}
-// Reg should be a 32-bit GPR. Return true if it is a high register rather
-// than a low register.
-static bool isHighReg(unsigned int Reg) {
- if (SystemZ::GRH32BitRegClass.contains(Reg))
- return true;
- assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
- return false;
-}
-
// Pin the vtable to this file.
void SystemZInstrInfo::anchor() {}
unsigned HighOpcode,
bool ConvertHigh) const {
Register Reg = MI.getOperand(0).getReg();
- bool IsHigh = isHighReg(Reg);
+ bool IsHigh = SystemZ::isHighReg(Reg);
MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
if (IsHigh && ConvertHigh)
MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
unsigned HighOpcode) const {
Register DestReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
- bool DestIsHigh = isHighReg(DestReg);
- bool SrcIsHigh = isHighReg(SrcReg);
+ bool DestIsHigh = SystemZ::isHighReg(DestReg);
+ bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
if (!DestIsHigh && !SrcIsHigh)
MI.setDesc(get(LowOpcodeK));
else {
void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
unsigned HighOpcode) const {
Register Reg = MI.getOperand(0).getReg();
- unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
- MI.getOperand(2).getImm());
+ unsigned Opcode = getOpcodeForOffset(
+ SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
+ MI.getOperand(2).getImm());
MI.setDesc(get(Opcode));
}
void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
unsigned HighOpcode) const {
Register Reg = MI.getOperand(0).getReg();
- unsigned Opcode = isHighReg(Reg) ? HighOpcode : LowOpcode;
+ unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
MI.setDesc(get(Opcode));
}
-// MI is a load-register-on-condition pseudo instruction. Replace it with
-// LowOpcode if source and destination are both low GR32s and HighOpcode if
-// source and destination are both high GR32s.
-void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
- unsigned HighOpcode) const {
- Register DestReg = MI.getOperand(0).getReg();
- Register SrcReg = MI.getOperand(2).getReg();
- bool DestIsHigh = isHighReg(DestReg);
- bool SrcIsHigh = isHighReg(SrcReg);
-
- if (!DestIsHigh && !SrcIsHigh)
- MI.setDesc(get(LowOpcode));
- else if (DestIsHigh && SrcIsHigh)
- MI.setDesc(get(HighOpcode));
- else
- LOCRMuxJumps++;
-
- // If we were unable to implement the pseudo with a single instruction, we
- // need to convert it back into a branch sequence. This cannot be done here
- // since the caller of expandPostRAPseudo does not handle changes to the CFG
- // correctly. This change is defered to the SystemZExpandPseudo pass.
-}
-
-// MI is a select pseudo instruction. Replace it with LowOpcode if source
-// and destination are all low GR32s and HighOpcode if source and destination
-// are all high GR32s. Otherwise, use the two-operand MixedOpcode.
-void SystemZInstrInfo::expandSELRPseudo(MachineInstr &MI, unsigned LowOpcode,
- unsigned HighOpcode,
- unsigned MixedOpcode) const {
- Register DestReg = MI.getOperand(0).getReg();
- Register Src1Reg = MI.getOperand(1).getReg();
- Register Src2Reg = MI.getOperand(2).getReg();
- bool DestIsHigh = isHighReg(DestReg);
- bool Src1IsHigh = isHighReg(Src1Reg);
- bool Src2IsHigh = isHighReg(Src2Reg);
-
- // If sources and destination aren't all high or all low, we may be able to
- // simplify the operation by moving one of the sources to the destination
- // first. But only if this doesn't clobber the other source.
- if (DestReg != Src1Reg && DestReg != Src2Reg) {
- if (DestIsHigh != Src1IsHigh) {
- emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, Src1Reg,
- SystemZ::LR, 32, MI.getOperand(1).isKill(),
- MI.getOperand(1).isUndef());
- MI.getOperand(1).setReg(DestReg);
- Src1Reg = DestReg;
- Src1IsHigh = DestIsHigh;
- } else if (DestIsHigh != Src2IsHigh) {
- emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, Src2Reg,
- SystemZ::LR, 32, MI.getOperand(2).isKill(),
- MI.getOperand(2).isUndef());
- MI.getOperand(2).setReg(DestReg);
- Src2Reg = DestReg;
- Src2IsHigh = DestIsHigh;
- }
- }
-
- // If the destination (now) matches one source, prefer this to be first.
- if (DestReg != Src1Reg && DestReg == Src2Reg) {
- commuteInstruction(MI, false, 1, 2);
- std::swap(Src1Reg, Src2Reg);
- std::swap(Src1IsHigh, Src2IsHigh);
- }
-
- if (!DestIsHigh && !Src1IsHigh && !Src2IsHigh)
- MI.setDesc(get(LowOpcode));
- else if (DestIsHigh && Src1IsHigh && Src2IsHigh)
- MI.setDesc(get(HighOpcode));
- else {
- // Given the simplifcation above, we must already have a two-operand case.
- assert (DestReg == Src1Reg);
- MI.setDesc(get(MixedOpcode));
- MI.tieOperands(0, 1);
- LOCRMuxJumps++;
- }
-
- // If we were unable to implement the pseudo with a single instruction, we
- // need to convert it back into a branch sequence. This cannot be done here
- // since the caller of expandPostRAPseudo does not handle changes to the CFG
- // correctly. This change is defered to the SystemZExpandPseudo pass.
-}
-
// MI is an RR-style pseudo instruction that zero-extends the low Size bits
// of one GRX32 into another. Replace it with LowOpcode if both operands
// are low registers, otherwise use RISB[LH]G.
unsigned Size, bool KillSrc,
bool UndefSrc) const {
unsigned Opcode;
- bool DestIsHigh = isHighReg(DestReg);
- bool SrcIsHigh = isHighReg(SrcReg);
+ bool DestIsHigh = SystemZ::isHighReg(DestReg);
+ bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
if (DestIsHigh && SrcIsHigh)
Opcode = SystemZ::RISBHH;
else if (DestIsHigh && !SrcIsHigh)
expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
return true;
- case SystemZ::LOCRMux:
- expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
- return true;
-
- case SystemZ::SELRMux:
- expandSELRPseudo(MI, SystemZ::SELR, SystemZ::SELFHR,
- SystemZ::LOCRMux);
- return true;
-
case SystemZ::STCMux:
expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
return true;
return true;
case SystemZ::RISBMux: {
- bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
- bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
+ bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
+ bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
if (SrcIsHigh == DestIsHigh)
MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
else {
unsigned HighOpcode) const;
void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
unsigned HighOpcode) const;
- void expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
- unsigned HighOpcode) const;
- void expandSELRPseudo(MachineInstr &MI, unsigned LowOpcode,
- unsigned HighOpcode, unsigned MixedOpcode) const;
void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
unsigned Size) const;
void expandLoadStackGuard(MachineInstr *MI) const;
#define DEBUG_TYPE "systemz-postrewrite"
STATISTIC(MemFoldCopies, "Number of copies inserted before folded mem ops.");
+STATISTIC(LOCRMuxJumps, "Number of LOCRMux jump-sequences (lower is better)");
namespace llvm {
void initializeSystemZPostRewritePass(PassRegistry&);
StringRef getPassName() const override { return SYSTEMZ_POSTREWRITE_NAME; }
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.setPreservesAll();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
private:
+ void selectLOCRMux(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LowOpcode,
+ unsigned HighOpcode);
+ void selectSELRMux(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LowOpcode,
+ unsigned HighOpcode);
+ bool expandCondMove(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI);
bool selectMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI);
bool selectMBB(MachineBasicBlock &MBB);
return new SystemZPostRewrite();
}
+// MI is a load-register-on-condition pseudo instruction. Replace it with
+// LowOpcode if source and destination are both low GR32s and HighOpcode if
+// source and destination are both high GR32s. Otherwise, a branch sequence
+// is created.
+void SystemZPostRewrite::selectLOCRMux(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LowOpcode,
+ unsigned HighOpcode) {
+ Register DestReg = MBBI->getOperand(0).getReg();
+ Register SrcReg = MBBI->getOperand(2).getReg();
+ bool DestIsHigh = SystemZ::isHighReg(DestReg);
+ bool SrcIsHigh = SystemZ::isHighReg(SrcReg);
+
+ if (!DestIsHigh && !SrcIsHigh)
+ MBBI->setDesc(TII->get(LowOpcode));
+ else if (DestIsHigh && SrcIsHigh)
+ MBBI->setDesc(TII->get(HighOpcode));
+ else
+ expandCondMove(MBB, MBBI, NextMBBI);
+}
+
+// MI is a select pseudo instruction. Replace it with LowOpcode if source
+// and destination are all low GR32s and HighOpcode if source and destination
+// are all high GR32s. Otherwise, a branch sequence is created.
+void SystemZPostRewrite::selectSELRMux(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI,
+ unsigned LowOpcode,
+ unsigned HighOpcode) {
+ Register DestReg = MBBI->getOperand(0).getReg();
+ Register Src1Reg = MBBI->getOperand(1).getReg();
+ Register Src2Reg = MBBI->getOperand(2).getReg();
+ bool DestIsHigh = SystemZ::isHighReg(DestReg);
+ bool Src1IsHigh = SystemZ::isHighReg(Src1Reg);
+ bool Src2IsHigh = SystemZ::isHighReg(Src2Reg);
+
+ // If sources and destination aren't all high or all low, we may be able to
+ // simplify the operation by moving one of the sources to the destination
+ // first. But only if this doesn't clobber the other source.
+ if (DestReg != Src1Reg && DestReg != Src2Reg) {
+ if (DestIsHigh != Src1IsHigh) {
+ BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
+ TII->get(SystemZ::COPY), DestReg)
+ .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
+ MBBI->getOperand(1).setReg(DestReg);
+ Src1Reg = DestReg;
+ Src1IsHigh = DestIsHigh;
+ } else if (DestIsHigh != Src2IsHigh) {
+ BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
+ TII->get(SystemZ::COPY), DestReg)
+ .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
+ MBBI->getOperand(2).setReg(DestReg);
+ Src2Reg = DestReg;
+ Src2IsHigh = DestIsHigh;
+ }
+ }
+
+ // If the destination (now) matches one source, prefer this to be first.
+ if (DestReg != Src1Reg && DestReg == Src2Reg) {
+ TII->commuteInstruction(*MBBI, false, 1, 2);
+ std::swap(Src1Reg, Src2Reg);
+ std::swap(Src1IsHigh, Src2IsHigh);
+ }
+
+ if (!DestIsHigh && !Src1IsHigh && !Src2IsHigh)
+ MBBI->setDesc(TII->get(LowOpcode));
+ else if (DestIsHigh && Src1IsHigh && Src2IsHigh)
+ MBBI->setDesc(TII->get(HighOpcode));
+ else
+ // Given the simplification above, we must already have a two-operand case.
+ expandCondMove(MBB, MBBI, NextMBBI);
+}
+
+// Replace MBBI by a branch sequence that performs a conditional move of
+// operand 2 to the destination register. Operand 1 is expected to be the
+// same register as the destination.
+bool SystemZPostRewrite::expandCondMove(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
+ MachineFunction &MF = *MBB.getParent();
+ const BasicBlock *BB = MBB.getBasicBlock();
+ MachineInstr &MI = *MBBI;
+ DebugLoc DL = MI.getDebugLoc();
+ Register DestReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(2).getReg();
+ unsigned CCValid = MI.getOperand(3).getImm();
+ unsigned CCMask = MI.getOperand(4).getImm();
+ assert(DestReg == MI.getOperand(1).getReg() &&
+ "Expected destination and first source operand to be the same.");
+
+ LivePhysRegs LiveRegs(TII->getRegisterInfo());
+ LiveRegs.addLiveOuts(MBB);
+ for (auto I = std::prev(MBB.end()); I != MBBI; --I)
+ LiveRegs.stepBackward(*I);
+
+ // Splice MBB at MI, moving the rest of the block into RestMBB.
+ MachineBasicBlock *RestMBB = MF.CreateMachineBasicBlock(BB);
+ MF.insert(std::next(MachineFunction::iterator(MBB)), RestMBB);
+ RestMBB->splice(RestMBB->begin(), &MBB, MI, MBB.end());
+ RestMBB->transferSuccessors(&MBB);
+ for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
+ RestMBB->addLiveIn(*I);
+
+ // Create a new block MoveMBB to hold the move instruction.
+ MachineBasicBlock *MoveMBB = MF.CreateMachineBasicBlock(BB);
+ MF.insert(std::next(MachineFunction::iterator(MBB)), MoveMBB);
+ MoveMBB->addLiveIn(SrcReg);
+ for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
+ MoveMBB->addLiveIn(*I);
+
+ // At the end of MBB, create a conditional branch to RestMBB if the
+ // condition is false, otherwise fall through to MoveMBB.
+ BuildMI(&MBB, DL, TII->get(SystemZ::BRC))
+ .addImm(CCValid).addImm(CCMask ^ CCValid).addMBB(RestMBB);
+ MBB.addSuccessor(RestMBB);
+ MBB.addSuccessor(MoveMBB);
+
+ // In MoveMBB, emit an instruction to move SrcReg into DestReg,
+ // then fall through to RestMBB.
+ BuildMI(*MoveMBB, MoveMBB->end(), DL, TII->get(SystemZ::COPY), DestReg)
+ .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
+ MoveMBB->addSuccessor(RestMBB);
+
+ NextMBBI = MBB.end();
+ MI.eraseFromParent();
+ LOCRMuxJumps++;
+ return true;
+}
+
/// If MBBI references a pseudo instruction that should be selected here,
/// do it and return true. Otherwise return false.
bool SystemZPostRewrite::selectMI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- MachineBasicBlock::iterator &NextMBBI) {
+ MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator &NextMBBI) {
MachineInstr &MI = *MBBI;
unsigned Opcode = MI.getOpcode();
return true;
}
+ switch (Opcode) {
+ case SystemZ::LOCRMux:
+ selectLOCRMux(MBB, MBBI, NextMBBI, SystemZ::LOCR, SystemZ::LOCFHR);
+ return true;
+ case SystemZ::SELRMux:
+ selectSELRMux(MBB, MBBI, NextMBBI, SystemZ::SELR, SystemZ::SELFHR);
+ return true;
+ }
+
return false;
}
inline unsigned odd128(bool Is32bit) {
return Is32bit ? subreg_l32 : subreg_l64;
}
+
+// Reg should be a 32-bit GPR. Return true if it is a high register rather
+// than a low register.
+inline bool isHighReg(unsigned int Reg) {
+ if (SystemZ::GRH32BitRegClass.contains(Reg))
+ return true;
+ assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
+ return false;
+}
} // end namespace SystemZ
struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
if (getOptLevel() == CodeGenOpt::None)
addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
- addPass(createSystemZExpandPseudoPass(getSystemZTargetMachine()));
-
if (getOptLevel() != CodeGenOpt::None)
addPass(&IfConverterID);
}
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