[NVPTX] Add NVPTX register constraints

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@184578 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 744a437fde5d0556a536186c5a7bcf84e9c762c7..737dd873b6210b4100456600609b3c890b66079e 100644 (file)
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -1290,9 +1290,18 @@ namespace {
       NumAliases = 0;
     }
     virtual bool validateAsmConstraint(const char *&Name,
-                                       TargetInfo::ConstraintInfo &info) const {
-      // FIXME: implement
-      return true;
+                                       TargetInfo::ConstraintInfo &Info) const {
+      switch (*Name) {
+      default: return false;
+      case 'c':
+      case 'h':
+      case 'r':
+      case 'l':
+      case 'f':
+      case 'd':
+        Info.setAllowsRegister();
+        return true;
+      }
     }
     virtual const char *getClobbers() const {
       // FIXME: Is this really right?

diff --git a/test/CodeGen/nvptx-inlineasm-ptx.c b/test/CodeGen/nvptx-inlineasm-ptx.c
new file mode 100644 (file)
index 0000000..8432e6c
--- /dev/null
+++ b/test/CodeGen/nvptx-inlineasm-ptx.c
@@ -0,0 +1,40 @@
+// RUN: %clang_cc1 -triple nvptx-unknown-unknown -O3 -S -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple nvptx64-unknown-unknown -O3 -S -o - %s | FileCheck %s
+
+void constraints() {
+  char           c;
+  unsigned char  uc;
+  short          s;
+  unsigned short us;
+  int            i;
+  unsigned int   ui;
+  long           l;
+  unsigned long  ul;
+  float          f;
+  double         d;
+
+  // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}}
+  asm volatile ("mov.b8 %0, %1;" : "=c"(c) : "c"(c));
+  // CHECK: mov.b8 %rc{{[0-9]+}}, %rc{{[0-9]+}}
+  asm volatile ("mov.b8 %0, %1;" : "=c"(uc) : "c"(uc));
+
+  // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}
+  asm volatile ("mov.b16 %0, %1;" : "=h"(s) : "h"(s));
+  // CHECK: mov.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}
+  asm volatile ("mov.b16 %0, %1;" : "=h"(us) : "h"(us));
+
+  // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}}
+  asm volatile ("mov.b32 %0, %1;" : "=r"(i) : "r"(i));
+  // CHECK: mov.b32 %r{{[0-9]+}}, %r{{[0-9]+}}
+  asm volatile ("mov.b32 %0, %1;" : "=r"(ui) : "r"(ui));
+
+  // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}
+  asm volatile ("mov.b64 %0, %1;" : "=l"(l) : "l"(l));
+  // CHECK: mov.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}
+  asm volatile ("mov.b64 %0, %1;" : "=l"(ul) : "l"(ul));
+
+  // CHECK: mov.b32 %f{{[0-9]+}}, %f{{[0-9]+}}
+  asm volatile ("mov.b32 %0, %1;" : "=f"(f) : "f"(f));
+  // CHECK: mov.b64 %fl{{[0-9]+}}, %fl{{[0-9]+}}
+  asm volatile ("mov.b64 %0, %1;" : "=d"(d) : "d"(d));
+}