[AArch64] Improve the Exynos M3 pipeline model

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349652 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SchedExynosM3.td b/lib/Target/AArch64/AArch64SchedExynosM3.td
index fd19ff84f1e010d40b16fdc6917d003bc3fb985b..6ffaf0f4a31f845a85b6c073986933c8b03c0f10 100644 (file)
--- a/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -162,8 +162,8 @@ def M3WriteLE : SchedWriteRes<[M3UnitA,
                                            let NumMicroOps = 2; }
 def M3WriteLH : SchedWriteRes<[]>        { let Latency = 5;
                                            let NumMicroOps = 0; }
-def M3WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M3WriteL5]>,
-                                   SchedVar<NoSchedPred,   [M3WriteL4]>]>;
+def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
+                                   SchedVar<NoSchedPred,         [M3WriteL4]>]>;
 
 def M3WriteS1 : SchedWriteRes<[M3UnitS]>   { let Latency = 1; }
 def M3WriteSA : SchedWriteRes<[M3UnitA,
@@ -174,8 +174,8 @@ def M3WriteSB : SchedWriteRes<[M3UnitA,
                                M3UnitS]>   { let Latency = 2;
                                              let NumMicroOps = 2; }
 
-def M3ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
-                                      SchedVar<NoSchedPred,   [ReadDefault]>]>;
+def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
+                                      SchedVar<NoSchedPred,         [ReadDefault]>]>;
 
 // Branch instructions.
 def : SchedAlias<WriteBr, M3WriteZ0>;

diff --git a/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s b/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s
index e93f738db37d5b2928e368826e029313e6c56dab..030a689b6e685cd0532e027f912ff3fcf41c7262 100644 (file)
--- a/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s
+++ b/test/tools/llvm-mca/AArch64/Exynos/load-register-offset.s
@@ -50,7 +50,7 @@
 # EM1-NEXT:  1      5     1.00    *                   ldr      d21, [x22, x23, lsl #3]
 # EM1-NEXT:  2      6     2.00    *                   ldr      q24, [x25, x26, lsl #4]
 
-# EM3-NEXT:  1      5     0.50    *                   ldrb     w0, [x1, x2, lsl #0]
+# EM3-NEXT:  1      4     0.50    *                   ldrb     w0, [x1, x2, lsl #0]
 # EM3-NEXT:  1      5     0.50    *                   ldrh     w3, [x4, x5, sxtx #1]
 # EM3-NEXT:  2      5     0.50    *                   ldr      w6, [x7, w8, uxtw #2]
 # EM3-NEXT:  2      5     0.50    *                   ldr      x9, [x10, w11, sxtw #3]