]> granicus.if.org Git - llvm/commitdiff
[X86] Add register form of NOPL and NOPW for assembler/disassembler.
authorCraig Topper <craig.topper@intel.com>
Sat, 22 Jul 2017 01:30:51 +0000 (01:30 +0000)
committerCraig Topper <craig.topper@intel.com>
Sat, 22 Jul 2017 01:30:51 +0000 (01:30 +0000)
Fixes PR32805.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308817 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrInfo.td
test/MC/Disassembler/X86/x86-32.txt
test/MC/X86/x86-32-coverage.s

index fab70e918b8adbb93208bc9379b70adb84b05959..700a9c0da7962ee2d09ee8e46a9587b3b84be820 100644 (file)
@@ -1108,6 +1108,11 @@ let hasSideEffects = 0, SchedRW = [WriteZero] in {
                 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
   def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
                 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
+  // Also allow register so we can assemble/disassemble
+  def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero),
+                 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
+  def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero),
+                 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
 }
 
 
index 1b865d37bf0bc30c4c4a21a308c18aa557bf69d3..5a09550a70850ff65a02a94d9e2045d75967083b 100644 (file)
 
 # CHECK: lwpval $2309737967, (%esp), %edx
 0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89
+
+# CHECK: nopl %eax
+0x0f 0x1f 0xc0
+
+# CHECK: nopw %ax
+0x66 0x0f 0x1f 0xc0
index c4f649ff4f4b4a2857b59f6dc5c706e78a2bb687..706039a7a2156f0a519fcbff01fda16b7898aa15 100644 (file)
 // CHECK:  encoding: [0x0f,0x1f,0x05,0x78,0x56,0x34,0x12]
                nopl    0x12345678
 
+// CHECK: nopw %ax
+// CHECK:  encoding: [0x66,0x0f,0x1f,0xc0]
+               nopw    %ax
+
+// CHECK: nopl %eax
+// CHECK:  encoding: [0x0f,0x1f,0xc0]
+               nopl    %eax
+
 // CHECK: nop
 // CHECK:  encoding: [0x90]
                nop